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@@ -541,3 +541,61 @@ static void __init omap_hsmmc_init_one(struct omap2_hsmmc_info *hsmmcinfo,
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goto free_mmc;
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res = omap_device_register(pdev);
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+ if (res) {
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+ pr_err("Could not register od for %s\n", name);
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+ goto free_od;
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+ }
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+
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+ goto free_mmc;
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+
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+free_od:
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+ omap_device_delete(od);
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+
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+put_pdev:
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+ platform_device_put(pdev);
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+
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+free_name:
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+ kfree(mmc_data->slots[0].name);
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+
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+free_mmc:
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+ kfree(mmc_data);
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+}
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+
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+void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
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+{
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+ u32 reg;
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+
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+ if (omap_hsmmc_done)
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+ return;
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+
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+ omap_hsmmc_done = 1;
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+
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+ if (!cpu_is_omap44xx()) {
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+ if (cpu_is_omap2430()) {
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+ control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
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+ control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
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+ } else {
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+ control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
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+ control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
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+ }
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+ } else {
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+ control_pbias_offset =
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+ OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
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+ control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
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+ reg = omap4_ctrl_pad_readl(control_mmc1);
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+ reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
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+ OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
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+ reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
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+ OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
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+ reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
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+ OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
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+ OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
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+ omap4_ctrl_pad_writel(reg, control_mmc1);
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+ }
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+
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+ for (; controllers->mmc; controllers++)
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+ omap_hsmmc_init_one(controllers, controllers->mmc);
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+
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+}
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+
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+#endif
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