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@@ -358,3 +358,45 @@ int __init omap4_mpuss_init(void)
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/* Initialise CPU0 power domain state to ON */
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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+ pm_info = &per_cpu(omap4_pm_info, 0x1);
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+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
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+ pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
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+ if (cpu_is_omap446x())
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+ pm_info->secondary_startup = omap_secondary_startup_4460;
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+ else
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+ pm_info->secondary_startup = omap_secondary_startup;
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+
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+ pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
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+ if (!pm_info->pwrdm) {
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+ pr_err("Lookup failed for CPU1 pwrdm\n");
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+ return -ENODEV;
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+ }
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+
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+ /* Clear CPU previous power domain state */
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+ pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
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+ cpu_clear_prev_logic_pwrst(1);
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+
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+ /* Initialise CPU1 power domain state to ON */
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+ pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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+
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+ mpuss_pd = pwrdm_lookup("mpu_pwrdm");
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+ if (!mpuss_pd) {
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+ pr_err("Failed to lookup MPUSS power domain\n");
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+ return -ENODEV;
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+ }
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+ pwrdm_clear_all_prev_pwrst(mpuss_pd);
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+ mpuss_clear_prev_logic_pwrst();
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+
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+ /* Save device type on scratchpad for low level code to use */
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+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
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+ __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
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+ else
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+ __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
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+
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+ save_l2x0_context();
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+
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+ return 0;
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+}
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+
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+#endif
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