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@@ -951,3 +951,180 @@
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/* DMA Channel 17 Registers */
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+#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
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+#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
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+#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR, val)
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+#define bfin_read_DMA17_CONFIG() bfin_read32(DMA17_CONFIG)
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+#define bfin_write_DMA17_CONFIG(val) bfin_write32(DMA17_CONFIG, val)
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+#define bfin_read_DMA17_X_COUNT() bfin_read32(DMA17_X_COUNT)
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+#define bfin_write_DMA17_X_COUNT(val) bfin_write32(DMA17_X_COUNT, val)
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+#define bfin_read_DMA17_X_MODIFY() bfin_read32(DMA17_X_MODIFY)
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+#define bfin_write_DMA17_X_MODIFY(val) bfin_write32(DMA17_X_MODIFY, val)
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+#define bfin_read_DMA17_Y_COUNT() bfin_read32(DMA17_Y_COUNT)
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+#define bfin_write_DMA17_Y_COUNT(val) bfin_write32(DMA17_Y_COUNT, val)
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+#define bfin_read_DMA17_Y_MODIFY() bfin_read32(DMA17_Y_MODIFY)
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+#define bfin_write_DMA17_Y_MODIFY(val) bfin_write32(DMA17_Y_MODIFY, val)
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+#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
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+#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR, val)
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+#define bfin_read_DMA17_PREV_DESC_PTR() bfin_read32(DMA17_PREV_DESC_PTR)
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+#define bfin_write_DMA17_PREV_DESC_PTR(val) bfin_write32(DMA17_PREV_DESC_PTR, val)
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+#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
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+#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR, val)
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+#define bfin_read_DMA17_IRQ_STATUS() bfin_read32(DMA17_IRQ_STATUS)
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+#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write32(DMA17_IRQ_STATUS, val)
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+#define bfin_read_DMA17_CURR_X_COUNT() bfin_read32(DMA17_CURR_X_COUNT)
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+#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write32(DMA17_CURR_X_COUNT, val)
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+#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read32(DMA17_CURR_Y_COUNT)
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+#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write32(DMA17_CURR_Y_COUNT, val)
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+#define bfin_read_DMA17_BWL_COUNT() bfin_read32(DMA17_BWL_COUNT)
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+#define bfin_write_DMA17_BWL_COUNT(val) bfin_write32(DMA17_BWL_COUNT, val)
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+#define bfin_read_DMA17_CURR_BWL_COUNT() bfin_read32(DMA17_CURR_BWL_COUNT)
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+#define bfin_write_DMA17_CURR_BWL_COUNT(val) bfin_write32(DMA17_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA17_BWM_COUNT() bfin_read32(DMA17_BWM_COUNT)
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+#define bfin_write_DMA17_BWM_COUNT(val) bfin_write32(DMA17_BWM_COUNT, val)
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+#define bfin_read_DMA17_CURR_BWM_COUNT() bfin_read32(DMA17_CURR_BWM_COUNT)
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+#define bfin_write_DMA17_CURR_BWM_COUNT(val) bfin_write32(DMA17_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 18 Registers */
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+
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+#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
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+#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
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+#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR, val)
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+#define bfin_read_DMA18_CONFIG() bfin_read32(DMA18_CONFIG)
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+#define bfin_write_DMA18_CONFIG(val) bfin_write32(DMA18_CONFIG, val)
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+#define bfin_read_DMA18_X_COUNT() bfin_read32(DMA18_X_COUNT)
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+#define bfin_write_DMA18_X_COUNT(val) bfin_write32(DMA18_X_COUNT, val)
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+#define bfin_read_DMA18_X_MODIFY() bfin_read32(DMA18_X_MODIFY)
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+#define bfin_write_DMA18_X_MODIFY(val) bfin_write32(DMA18_X_MODIFY, val)
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+#define bfin_read_DMA18_Y_COUNT() bfin_read32(DMA18_Y_COUNT)
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+#define bfin_write_DMA18_Y_COUNT(val) bfin_write32(DMA18_Y_COUNT, val)
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+#define bfin_read_DMA18_Y_MODIFY() bfin_read32(DMA18_Y_MODIFY)
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+#define bfin_write_DMA18_Y_MODIFY(val) bfin_write32(DMA18_Y_MODIFY, val)
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+#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
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+#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR, val)
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+#define bfin_read_DMA18_PREV_DESC_PTR() bfin_read32(DMA18_PREV_DESC_PTR)
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+#define bfin_write_DMA18_PREV_DESC_PTR(val) bfin_write32(DMA18_PREV_DESC_PTR, val)
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+#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
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+#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR, val)
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+#define bfin_read_DMA18_IRQ_STATUS() bfin_read32(DMA18_IRQ_STATUS)
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+#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write32(DMA18_IRQ_STATUS, val)
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+#define bfin_read_DMA18_CURR_X_COUNT() bfin_read32(DMA18_CURR_X_COUNT)
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+#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write32(DMA18_CURR_X_COUNT, val)
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+#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read32(DMA18_CURR_Y_COUNT)
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+#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write32(DMA18_CURR_Y_COUNT, val)
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+#define bfin_read_DMA18_BWL_COUNT() bfin_read32(DMA18_BWL_COUNT)
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+#define bfin_write_DMA18_BWL_COUNT(val) bfin_write32(DMA18_BWL_COUNT, val)
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+#define bfin_read_DMA18_CURR_BWL_COUNT() bfin_read32(DMA18_CURR_BWL_COUNT)
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+#define bfin_write_DMA18_CURR_BWL_COUNT(val) bfin_write32(DMA18_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA18_BWM_COUNT() bfin_read32(DMA18_BWM_COUNT)
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+#define bfin_write_DMA18_BWM_COUNT(val) bfin_write32(DMA18_BWM_COUNT, val)
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+#define bfin_read_DMA18_CURR_BWM_COUNT() bfin_read32(DMA18_CURR_BWM_COUNT)
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+#define bfin_write_DMA18_CURR_BWM_COUNT(val) bfin_write32(DMA18_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 19 Registers */
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+
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+#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
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+#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
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+#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR, val)
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+#define bfin_read_DMA19_CONFIG() bfin_read32(DMA19_CONFIG)
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+#define bfin_write_DMA19_CONFIG(val) bfin_write32(DMA19_CONFIG, val)
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+#define bfin_read_DMA19_X_COUNT() bfin_read32(DMA19_X_COUNT)
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+#define bfin_write_DMA19_X_COUNT(val) bfin_write32(DMA19_X_COUNT, val)
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+#define bfin_read_DMA19_X_MODIFY() bfin_read32(DMA19_X_MODIFY)
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+#define bfin_write_DMA19_X_MODIFY(val) bfin_write32(DMA19_X_MODIFY, val)
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+#define bfin_read_DMA19_Y_COUNT() bfin_read32(DMA19_Y_COUNT)
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+#define bfin_write_DMA19_Y_COUNT(val) bfin_write32(DMA19_Y_COUNT, val)
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+#define bfin_read_DMA19_Y_MODIFY() bfin_read32(DMA19_Y_MODIFY)
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+#define bfin_write_DMA19_Y_MODIFY(val) bfin_write32(DMA19_Y_MODIFY, val)
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+#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
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+#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR, val)
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+#define bfin_read_DMA19_PREV_DESC_PTR() bfin_read32(DMA19_PREV_DESC_PTR)
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+#define bfin_write_DMA19_PREV_DESC_PTR(val) bfin_write32(DMA19_PREV_DESC_PTR, val)
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+#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
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+#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR, val)
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+#define bfin_read_DMA19_IRQ_STATUS() bfin_read32(DMA19_IRQ_STATUS)
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+#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write32(DMA19_IRQ_STATUS, val)
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+#define bfin_read_DMA19_CURR_X_COUNT() bfin_read32(DMA19_CURR_X_COUNT)
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+#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write32(DMA19_CURR_X_COUNT, val)
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+#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read32(DMA19_CURR_Y_COUNT)
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+#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write32(DMA19_CURR_Y_COUNT, val)
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+#define bfin_read_DMA19_BWL_COUNT() bfin_read32(DMA19_BWL_COUNT)
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+#define bfin_write_DMA19_BWL_COUNT(val) bfin_write32(DMA19_BWL_COUNT, val)
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+#define bfin_read_DMA19_CURR_BWL_COUNT() bfin_read32(DMA19_CURR_BWL_COUNT)
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+#define bfin_write_DMA19_CURR_BWL_COUNT(val) bfin_write32(DMA19_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA19_BWM_COUNT() bfin_read32(DMA19_BWM_COUNT)
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+#define bfin_write_DMA19_BWM_COUNT(val) bfin_write32(DMA19_BWM_COUNT, val)
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+#define bfin_read_DMA19_CURR_BWM_COUNT() bfin_read32(DMA19_CURR_BWM_COUNT)
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+#define bfin_write_DMA19_CURR_BWM_COUNT(val) bfin_write32(DMA19_CURR_BWM_COUNT, val)
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+
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+/* DMA Channel 20 Registers */
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+
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+#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
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+#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR, val)
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+#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
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+#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR, val)
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+#define bfin_read_DMA20_CONFIG() bfin_read32(DMA20_CONFIG)
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+#define bfin_write_DMA20_CONFIG(val) bfin_write32(DMA20_CONFIG, val)
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+#define bfin_read_DMA20_X_COUNT() bfin_read32(DMA20_X_COUNT)
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+#define bfin_write_DMA20_X_COUNT(val) bfin_write32(DMA20_X_COUNT, val)
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+#define bfin_read_DMA20_X_MODIFY() bfin_read32(DMA20_X_MODIFY)
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+#define bfin_write_DMA20_X_MODIFY(val) bfin_write32(DMA20_X_MODIFY, val)
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+#define bfin_read_DMA20_Y_COUNT() bfin_read32(DMA20_Y_COUNT)
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+#define bfin_write_DMA20_Y_COUNT(val) bfin_write32(DMA20_Y_COUNT, val)
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+#define bfin_read_DMA20_Y_MODIFY() bfin_read32(DMA20_Y_MODIFY)
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+#define bfin_write_DMA20_Y_MODIFY(val) bfin_write32(DMA20_Y_MODIFY, val)
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+#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
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+#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR, val)
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+#define bfin_read_DMA20_PREV_DESC_PTR() bfin_read32(DMA20_PREV_DESC_PTR)
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+#define bfin_write_DMA20_PREV_DESC_PTR(val) bfin_write32(DMA20_PREV_DESC_PTR, val)
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+#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
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+#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR, val)
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+#define bfin_read_DMA20_IRQ_STATUS() bfin_read32(DMA20_IRQ_STATUS)
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+#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write32(DMA20_IRQ_STATUS, val)
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+#define bfin_read_DMA20_CURR_X_COUNT() bfin_read32(DMA20_CURR_X_COUNT)
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+#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write32(DMA20_CURR_X_COUNT, val)
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+#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read32(DMA20_CURR_Y_COUNT)
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+#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write32(DMA20_CURR_Y_COUNT, val)
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+#define bfin_read_DMA20_BWL_COUNT() bfin_read32(DMA20_BWL_COUNT)
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+#define bfin_write_DMA20_BWL_COUNT(val) bfin_write32(DMA20_BWL_COUNT, val)
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+#define bfin_read_DMA20_CURR_BWL_COUNT() bfin_read32(DMA20_CURR_BWL_COUNT)
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+#define bfin_write_DMA20_CURR_BWL_COUNT(val) bfin_write32(DMA20_CURR_BWL_COUNT, val)
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+#define bfin_read_DMA20_BWM_COUNT() bfin_read32(DMA20_BWM_COUNT)
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+#define bfin_write_DMA20_BWM_COUNT(val) bfin_write32(DMA20_BWM_COUNT, val)
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+#define bfin_read_DMA20_CURR_BWM_COUNT() bfin_read32(DMA20_CURR_BWM_COUNT)
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+#define bfin_write_DMA20_CURR_BWM_COUNT(val) bfin_write32(DMA20_CURR_BWM_COUNT, val)
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+
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+
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+/* MDMA Stream 0 Registers (DMA Channel 21 and 22) */
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+
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+#define bfin_read_MDMA0_DEST_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_NEXT_DESC_PTR)
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+#define bfin_write_MDMA0_DEST_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_NEXT_DESC_PTR, val)
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+#define bfin_read_MDMA0_DEST_CRC0_START_ADDR() bfin_read32(MDMA0_DEST_CRC0_START_ADDR)
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+#define bfin_write_MDMA0_DEST_CRC0_START_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_START_ADDR, val)
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+#define bfin_read_MDMA0_DEST_CRC0_CONFIG() bfin_read32(MDMA0_DEST_CRC0_CONFIG)
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+#define bfin_write_MDMA0_DEST_CRC0_CONFIG(val) bfin_write32(MDMA0_DEST_CRC0_CONFIG, val)
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+#define bfin_read_MDMA0_DEST_CRC0_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_X_COUNT)
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+#define bfin_write_MDMA0_DEST_CRC0_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_X_COUNT, val)
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+#define bfin_read_MDMA0_DEST_CRC0_X_MODIFY() bfin_read32(MDMA0_DEST_CRC0_X_MODIFY)
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+#define bfin_write_MDMA0_DEST_CRC0_X_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_X_MODIFY, val)
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+#define bfin_read_MDMA0_DEST_CRC0_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_Y_COUNT)
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+#define bfin_write_MDMA0_DEST_CRC0_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_Y_COUNT, val)
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+#define bfin_read_MDMA0_DEST_CRC0_Y_MODIFY() bfin_read32(MDMA0_DEST_CRC0_Y_MODIFY)
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+#define bfin_write_MDMA0_DEST_CRC0_Y_MODIFY(val) bfin_write32(MDMA0_DEST_CRC0_Y_MODIFY, val)
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+#define bfin_read_MDMA0_DEST_CRC0_CURR_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_CURR_DESC_PTR)
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+#define bfin_write_MDMA0_DEST_CRC0_CURR_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_DESC_PTR, val)
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+#define bfin_read_MDMA0_DEST_CRC0_PREV_DESC_PTR() bfin_read32(MDMA0_DEST_CRC0_PREV_DESC_PTR)
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+#define bfin_write_MDMA0_DEST_CRC0_PREV_DESC_PTR(val) bfin_write32(MDMA0_DEST_CRC0_PREV_DESC_PTR, val)
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+#define bfin_read_MDMA0_DEST_CRC0_CURR_ADDR() bfin_read32(MDMA0_DEST_CRC0_CURR_ADDR)
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+#define bfin_write_MDMA0_DEST_CRC0_CURR_ADDR(val) bfin_write32(MDMA0_DEST_CRC0_CURR_ADDR, val)
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+#define bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS() bfin_read32(MDMA0_DEST_CRC0_IRQ_STATUS)
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+#define bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS(val) bfin_write32(MDMA0_DEST_CRC0_IRQ_STATUS, val)
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+#define bfin_read_MDMA0_DEST_CRC0_CURR_X_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_X_COUNT)
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+#define bfin_write_MDMA0_DEST_CRC0_CURR_X_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_X_COUNT, val)
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+#define bfin_read_MDMA0_DEST_CRC0_CURR_Y_COUNT() bfin_read32(MDMA0_DEST_CRC0_CURR_Y_COUNT)
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+#define bfin_write_MDMA0_DEST_CRC0_CURR_Y_COUNT(val) bfin_write32(MDMA0_DEST_CRC0_CURR_Y_COUNT, val)
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+#define bfin_read_MDMA0_SRC_CRC0_NEXT_DESC_PTR() bfin_read32(MDMA0_SRC_CRC0_NEXT_DESC_PTR)
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+#define bfin_write_MDMA0_SRC_CRC0_NEXT_DESC_PTR(val) bfin_write32(MDMA0_SRC_CRC0_NEXT_DESC_PTR, val)
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袁明明