|
@@ -898,3 +898,122 @@ static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
|
|
|
*/
|
|
|
if (mux) {
|
|
|
temp = max_t(u32, temp,
|
|
|
+ gpmc_t->adv_wr_off + dev_t->t_aavdh);
|
|
|
+ temp = max_t(u32, temp, gpmc_t->adv_wr_off +
|
|
|
+ gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
|
|
|
+ }
|
|
|
+ gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ /* we_on */
|
|
|
+ if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
|
|
|
+ gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
|
|
|
+ else
|
|
|
+ gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
|
|
|
+
|
|
|
+ /* wr_access */
|
|
|
+ /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
|
|
|
+ gpmc_t->wr_access = gpmc_t->access;
|
|
|
+
|
|
|
+ /* we_off */
|
|
|
+ temp = gpmc_t->we_on + dev_t->t_wpl;
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->wr_access + gpmc_ticks_to_ps(1));
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
|
|
|
+ gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
|
|
|
+ dev_t->t_wph);
|
|
|
+
|
|
|
+ /* wr_cycle */
|
|
|
+ temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
|
|
|
+ temp += gpmc_t->wr_access;
|
|
|
+ /* XXX: barter t_ce_rdyz with t_cez_w ? */
|
|
|
+ if (dev_t->t_ce_rdyz)
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
|
|
|
+ gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
|
|
|
+ struct gpmc_device_timings *dev_t)
|
|
|
+{
|
|
|
+ bool mux = dev_t->mux;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ /* adv_rd_off */
|
|
|
+ temp = dev_t->t_avdp_r;
|
|
|
+ if (mux)
|
|
|
+ temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
|
|
|
+ gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ /* oe_on */
|
|
|
+ temp = dev_t->t_oeasu;
|
|
|
+ if (mux)
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->adv_rd_off + dev_t->t_aavdh);
|
|
|
+ gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ /* access */
|
|
|
+ temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
|
|
|
+ gpmc_t->oe_on + dev_t->t_oe);
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->cs_on + dev_t->t_ce);
|
|
|
+ temp = max_t(u32, temp,
|
|
|
+ gpmc_t->adv_on + dev_t->t_aa);
|
|
|
+ gpmc_t->access = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
|
|
|
+ gpmc_t->cs_rd_off = gpmc_t->oe_off;
|
|
|
+
|
|
|
+ /* rd_cycle */
|
|
|
+ temp = max_t(u32, dev_t->t_rd_cycle,
|
|
|
+ gpmc_t->cs_rd_off + dev_t->t_cez_r);
|
|
|
+ temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
|
|
|
+ gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
|
|
|
+ struct gpmc_device_timings *dev_t)
|
|
|
+{
|
|
|
+ bool mux = dev_t->mux;
|
|
|
+ u32 temp;
|
|
|
+
|
|
|
+ /* adv_wr_off */
|
|
|
+ temp = dev_t->t_avdp_w;
|
|
|
+ if (mux)
|
|
|
+ temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
|
|
|
+ gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ /* wr_data_mux_bus */
|
|
|
+ temp = dev_t->t_weasu;
|
|
|
+ if (mux) {
|
|
|
+ temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
|
|
|
+ temp = max_t(u32, temp, gpmc_t->adv_wr_off +
|
|
|
+ gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
|
|
|
+ }
|
|
|
+ gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ /* we_on */
|
|
|
+ if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
|
|
|
+ gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
|
|
|
+ else
|
|
|
+ gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
|
|
|
+
|
|
|
+ /* we_off */
|
|
|
+ temp = gpmc_t->we_on + dev_t->t_wpl;
|
|
|
+ gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
|
|
|
+ dev_t->t_wph);
|
|
|
+
|
|
|
+ /* wr_cycle */
|
|
|
+ temp = max_t(u32, dev_t->t_wr_cycle,
|
|
|
+ gpmc_t->cs_wr_off + dev_t->t_cez_w);
|
|
|
+ gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
|
|
|
+
|
|
|
+ return 0;
|