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@@ -190,3 +190,95 @@
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#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
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#define CIA_IOC_PCI_T0_BASE (IDENT_ADDR + 0x8760000480UL)
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#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
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#define CIA_IOC_PCI_W1_BASE (IDENT_ADDR + 0x8760000500UL)
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+#define CIA_IOC_PCI_W1_MASK (IDENT_ADDR + 0x8760000540UL)
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+#define CIA_IOC_PCI_T1_BASE (IDENT_ADDR + 0x8760000580UL)
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+
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+#define CIA_IOC_PCI_W2_BASE (IDENT_ADDR + 0x8760000600UL)
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+#define CIA_IOC_PCI_W2_MASK (IDENT_ADDR + 0x8760000640UL)
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+#define CIA_IOC_PCI_T2_BASE (IDENT_ADDR + 0x8760000680UL)
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+
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+#define CIA_IOC_PCI_W3_BASE (IDENT_ADDR + 0x8760000700UL)
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+#define CIA_IOC_PCI_W3_MASK (IDENT_ADDR + 0x8760000740UL)
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+#define CIA_IOC_PCI_T3_BASE (IDENT_ADDR + 0x8760000780UL)
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+
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+#define CIA_IOC_PCI_Wn_BASE(N) (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
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+#define CIA_IOC_PCI_Wn_MASK(N) (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
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+#define CIA_IOC_PCI_Tn_BASE(N) (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
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+
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+#define CIA_IOC_PCI_W_DAC (IDENT_ADDR + 0x87600007C0UL)
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+
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+/*
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+ * 2117A-CA Address Translation Registers.
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+ */
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+
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+/* 8 tag registers, the first 4 of which are lockable. */
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+#define CIA_IOC_TB_TAGn(n) \
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+ (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
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+
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+/* 4 page registers per tag register. */
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+#define CIA_IOC_TBn_PAGEm(n,m) \
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+ (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
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+
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+/*
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+ * Memory spaces:
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+ */
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+#define CIA_IACK_SC (IDENT_ADDR + 0x8720000000UL)
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+#define CIA_CONF (IDENT_ADDR + 0x8700000000UL)
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+#define CIA_IO (IDENT_ADDR + 0x8580000000UL)
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+#define CIA_SPARSE_MEM (IDENT_ADDR + 0x8000000000UL)
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+#define CIA_SPARSE_MEM_R2 (IDENT_ADDR + 0x8400000000UL)
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+#define CIA_SPARSE_MEM_R3 (IDENT_ADDR + 0x8500000000UL)
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+#define CIA_DENSE_MEM (IDENT_ADDR + 0x8600000000UL)
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+#define CIA_BW_MEM (IDENT_ADDR + 0x8800000000UL)
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+#define CIA_BW_IO (IDENT_ADDR + 0x8900000000UL)
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+#define CIA_BW_CFG_0 (IDENT_ADDR + 0x8a00000000UL)
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+#define CIA_BW_CFG_1 (IDENT_ADDR + 0x8b00000000UL)
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+
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+/*
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+ * ALCOR's GRU ASIC registers
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+ */
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+#define GRU_INT_REQ (IDENT_ADDR + 0x8780000000UL)
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+#define GRU_INT_MASK (IDENT_ADDR + 0x8780000040UL)
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+#define GRU_INT_EDGE (IDENT_ADDR + 0x8780000080UL)
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+#define GRU_INT_HILO (IDENT_ADDR + 0x87800000C0UL)
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+#define GRU_INT_CLEAR (IDENT_ADDR + 0x8780000100UL)
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+
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+#define GRU_CACHE_CNFG (IDENT_ADDR + 0x8780000200UL)
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+#define GRU_SCR (IDENT_ADDR + 0x8780000300UL)
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+#define GRU_LED (IDENT_ADDR + 0x8780000800UL)
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+#define GRU_RESET (IDENT_ADDR + 0x8780000900UL)
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+
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+#define ALCOR_GRU_INT_REQ_BITS 0x800fffffUL
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+#define XLT_GRU_INT_REQ_BITS 0x80003fffUL
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+#define GRU_INT_REQ_BITS (alpha_mv.sys.cia.gru_int_req_bits+0)
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+
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+/*
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+ * PYXIS interrupt control registers
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+ */
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+#define PYXIS_INT_REQ (IDENT_ADDR + 0x87A0000000UL)
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+#define PYXIS_INT_MASK (IDENT_ADDR + 0x87A0000040UL)
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+#define PYXIS_INT_HILO (IDENT_ADDR + 0x87A00000C0UL)
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+#define PYXIS_INT_ROUTE (IDENT_ADDR + 0x87A0000140UL)
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+#define PYXIS_GPO (IDENT_ADDR + 0x87A0000180UL)
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+#define PYXIS_INT_CNFG (IDENT_ADDR + 0x87A00001C0UL)
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+#define PYXIS_RT_COUNT (IDENT_ADDR + 0x87A0000200UL)
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+#define PYXIS_INT_TIME (IDENT_ADDR + 0x87A0000240UL)
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+#define PYXIS_IIC_CTRL (IDENT_ADDR + 0x87A00002C0UL)
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+#define PYXIS_RESET (IDENT_ADDR + 0x8780000900UL)
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+
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+/* Offset between ram physical addresses and pci64 DAC bus addresses. */
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+#define PYXIS_DAC_OFFSET (1UL << 40)
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+
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+/*
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+ * Data structure for handling CIA machine checks.
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+ */
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+
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+/* System-specific info. */
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+struct el_CIA_sysdata_mcheck {
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+ unsigned long cpu_err0;
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+ unsigned long cpu_err1;
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+ unsigned long cia_err;
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+ unsigned long cia_stat;
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+ unsigned long err_mask;
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+ unsigned long cia_syn;
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+ unsigned long mem_err0;
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