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@@ -172,3 +172,41 @@ int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
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* transfer start latency" here is defined as the elapsed time from
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* when a device (e.g., McBSP) requests that a system DMA transfer
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* start or continue, to the time at which data starts to flow into
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+ * that device from the system DMA controller.
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+ *
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+ * It is intended that underlying PM code will use this information to
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+ * determine what power state to put the CORE powerdomain into.
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+ *
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+ * Since system DMA transfers may not involve the MPU, this function
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+ * will not affect MPU wakeup latency. Use set_max_cpu_lat() to do
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+ * so. Similarly, this function will not affect device wakeup latency
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+ * -- use set_max_dev_wakeup_lat() to affect that.
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+ *
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+ * Multiple calls to set_max_sdma_lat() will replace the previous t
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+ * value for this device. To remove the maximum DMA latency for this
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+ * device, call with t = -1.
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+ *
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+ * Returns -EINVAL for an invalid argument, -ERANGE if the constraint
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+ * is not satisfiable, or 0 upon success.
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+ */
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+int omap_pm_set_max_sdma_lat(struct device *dev, long t);
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+
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+
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+/**
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+ * omap_pm_set_min_clk_rate - set minimum clock rate requested by @dev
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+ * @dev: struct device * requesting the constraint
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+ * @clk: struct clk * to set the minimum rate constraint on
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+ * @r: minimum rate in Hz
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+ *
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+ * Request that the minimum clock rate on the device @dev's clk @clk
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+ * be no less than @r Hz.
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+ *
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+ * It is expected that the OMAP PM code will use this information to
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+ * find an OPP or clock setting that will satisfy this clock rate
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+ * constraint, along with any other applicable system constraints on
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+ * the clock rate or corresponding voltage, etc.
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+ *
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+ * omap_pm_set_min_clk_rate() differs from the clock code's
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+ * clk_set_rate() in that it considers other constraints before taking
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+ * any hardware action, and may change a system OPP rather than just a
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+ * clock rate. clk_set_rate() is intended to be a low-level
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