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@@ -467,3 +467,59 @@ int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
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}
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/*
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+ * Sets the Omap MUX and PULL_DWN registers based on the table
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+ */
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+int __init_or_module omap_cfg_reg(const unsigned long index)
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+{
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+ struct pin_config *reg;
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+
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+ if (!cpu_class_is_omap1()) {
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+ printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
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+ index);
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+ WARN_ON(1);
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+ return -EINVAL;
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+ }
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+
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+ if (mux_cfg == NULL) {
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+ printk(KERN_ERR "Pin mux table not initialized\n");
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+ return -ENODEV;
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+ }
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+
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+ if (index >= mux_cfg->size) {
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+ printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
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+ index, mux_cfg->size);
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+ dump_stack();
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+ return -ENODEV;
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+ }
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+
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+ reg = &mux_cfg->pins[index];
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+
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+ if (!mux_cfg->cfg_reg)
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+ return -ENODEV;
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+
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+ return mux_cfg->cfg_reg(reg);
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+}
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+EXPORT_SYMBOL(omap_cfg_reg);
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+
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+int __init omap1_mux_init(void)
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+{
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+ if (cpu_is_omap7xx()) {
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+ arch_mux_cfg.pins = omap7xx_pins;
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+ arch_mux_cfg.size = OMAP7XX_PINS_SZ;
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+ arch_mux_cfg.cfg_reg = omap1_cfg_reg;
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+ }
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+
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+ if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
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+ arch_mux_cfg.pins = omap1xxx_pins;
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+ arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
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+ arch_mux_cfg.cfg_reg = omap1_cfg_reg;
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+ }
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+
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+ return omap_mux_register(&arch_mux_cfg);
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+}
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+
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+#else
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+#define omap_mux_init() do {} while(0)
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+#define omap_cfg_reg(x) do {} while(0)
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+#endif /* CONFIG_OMAP_MUX */
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+
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