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@@ -230,3 +230,61 @@
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#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
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#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
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#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
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+#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
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+#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
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+#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
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+#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
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+#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
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+#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
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+#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
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+#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
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+#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
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+#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
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+#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
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+#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
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+#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
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+#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
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+#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
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+#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
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+#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
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+#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
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+#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
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+#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
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+#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
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+#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
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+#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
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+#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
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+#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
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+#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
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+#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
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+#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
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+#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
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+#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
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+#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
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+#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
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+#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
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+#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
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+#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
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+#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
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+#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
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+#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
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+#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
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+#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
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+#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
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+#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
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+#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
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+#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
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+#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
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+#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
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+#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
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+#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
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+#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
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+#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
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+#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
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+#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
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+
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+#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
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+extern int mx50_revision(void);
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+#endif
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+
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+#endif /* ifndef __MACH_MX50_H__ */
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吉超博