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@@ -332,3 +332,118 @@ int __init mx6q_clocks_init(void)
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clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
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clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3);
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clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3);
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+ clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
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+ clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
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+
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+ /* name parent_name reg shift width busy: reg, shift */
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+ clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
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+ clk[mmdc_ch0_axi_podf] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
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+ clk[mmdc_ch1_axi_podf] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
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+ clk[arm] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
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+ clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
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+
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+ /* name parent_name reg shift */
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+ clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
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+ clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6);
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+ clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
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+ clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16);
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+ clk[can2_ipg] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
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+ clk[can2_serial] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20);
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+ clk[ecspi1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
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+ clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
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+ clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
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+ clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
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+ clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
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+ clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
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+ clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
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+ clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
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+ clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
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+ clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
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+ clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
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+ clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
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+ clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
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+ clk[i2c1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
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+ clk[i2c2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
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+ clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
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+ clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
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+ clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
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+ clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
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+ clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
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+ clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
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+ clk[ipu2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
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+ clk[ipu2_di0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
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+ clk[ldb_di0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
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+ clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
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+ clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
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+ clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
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+ clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
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+ clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
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+ clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
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+ clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
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+ clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30);
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+ clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
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+ clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
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+ clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16);
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+ clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18);
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+ clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20);
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+ clk[pwm4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22);
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+ clk[gpmi_bch_apb] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
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+ clk[gpmi_bch] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
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+ clk[gpmi_io] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28);
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+ clk[gpmi_apb] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
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+ clk[rom] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
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+ clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
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+ clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
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+ clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
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+ clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
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+ clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
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+ clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
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+ clk[uart_ipg] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
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+ clk[uart_serial] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
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+ clk[usboh3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
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+ clk[usdhc1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
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+ clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
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+ clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
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+ clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
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+ clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
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+ clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
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+ clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
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+
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+ for (i = 0; i < ARRAY_SIZE(clk); i++)
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+ if (IS_ERR(clk[i]))
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+ pr_err("i.MX6q clk %d: register failed with %ld\n",
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+ i, PTR_ERR(clk[i]));
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+
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+ clk_data.clks = clk;
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+ clk_data.clk_num = ARRAY_SIZE(clk);
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+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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+
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+ clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
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+ clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
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+ clk_register_clkdev(clk[twd], NULL, "smp_twd");
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+ clk_register_clkdev(clk[cko1_sel], "cko1_sel", NULL);
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+ clk_register_clkdev(clk[ahb], "ahb", NULL);
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+ clk_register_clkdev(clk[cko1], "cko1", NULL);
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+ clk_register_clkdev(clk[arm], NULL, "cpu0");
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+
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+ /*
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+ * The gpmi needs 100MHz frequency in the EDO/Sync mode,
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+ * We can not get the 100MHz from the pll2_pfd0_352m.
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+ * So choose pll2_pfd2_396m as enfc_sel's parent.
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+ */
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+ clk_set_parent(clk[enfc_sel], clk[pll2_pfd2_396m]);
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+
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+ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
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+ clk_prepare_enable(clk[clks_init_on[i]]);
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+
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+ /* Set initial power mode */
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+ imx6q_set_lpm(WAIT_CLOCKED);
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+
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+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
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+ base = of_iomap(np, 0);
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+ WARN_ON(!base);
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+ irq = irq_of_parse_and_map(np, 0);
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+ mxc_timer_init(base, irq);
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+
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+ return 0;
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+}
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