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@@ -130,3 +130,96 @@
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#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
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#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
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#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
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#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
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#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
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#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
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+#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
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+#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
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+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
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+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
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+#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
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+#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
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+#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
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+#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
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+#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128
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+#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
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+#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c
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+#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
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+#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130
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+#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
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+#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138
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+#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
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+#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c
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+#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
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+#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140
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+#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
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+#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
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+#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
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+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
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+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
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+#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
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+#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
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+#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
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+#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
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+#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
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+#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
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+#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180
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+#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
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+
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+/* CM1.MPU_CM1 register offsets */
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+#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000
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+#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
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+#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004
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+#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
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+#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008
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+#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
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+#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
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+#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
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+
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+/* CM1.TESLA_CM1 register offsets */
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+#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000
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+#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
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+#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004
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+#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
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+#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008
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+#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
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+#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020
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+#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
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+
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+/* CM1.ABE_CM1 register offsets */
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+#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000
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+#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
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+#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020
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+#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
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+#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028
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+#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
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+#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030
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+#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
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+#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038
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+#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
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+#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040
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+#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
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+#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048
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+#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
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+#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050
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+#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
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+#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058
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+#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
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+#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060
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+#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
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+#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068
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+#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
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+#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070
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+#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
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+#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078
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+#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
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+#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080
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+#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
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+#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
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+#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
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+
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+/* Function prototypes */
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+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
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+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
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+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
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+
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+#endif
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