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@@ -790,3 +790,81 @@
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#define USTCNT_TXHALFEN USTCNT_TXHE
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#define USTCNT_TXEMPTYEN USTCNT_TXEE
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#define USTCNT_RXREADYEN USTCNT_RXRE
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+#define USTCNT_RXHALFEN USTCNT_RXHE
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+#define USTCNT_RXFULLEN USTCNT_RXFE
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+#define USTCNT_CTSDELTAEN USTCNT_CTSD
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+#define USTCNT_ODD_EVEN USTCNT_ODD
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+#define USTCNT_PARITYEN USTCNT_PEN
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+#define USTCNT_CLKMODE USTCNT_CLKM
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+#define USTCNT_UARTEN USTCNT_UEN
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+
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+/*
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+ * UART Baud Control Register
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+ */
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+#define UBAUD_ADDR 0xfffff902
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+#define UBAUD WORD_REF(UBAUD_ADDR)
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+
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+#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
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+#define UBAUD_PRESCALER_SHIFT 0
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+#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
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+#define UBAUD_DIVIDE_SHIFT 8
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+#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
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+#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
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+
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+/*
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+ * UART Receiver Register
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+ */
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+#define URX_ADDR 0xfffff904
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+#define URX WORD_REF(URX_ADDR)
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+
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+#define URX_RXDATA_ADDR 0xfffff905
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+#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR)
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+
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+#define URX_RXDATA_MASK 0x00ff /* Received data */
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+#define URX_RXDATA_SHIFT 0
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+#define URX_PARITY_ERROR 0x0100 /* Parity Error */
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+#define URX_BREAK 0x0200 /* Break Detected */
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+#define URX_FRAME_ERROR 0x0400 /* Framing Error */
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+#define URX_OVRUN 0x0800 /* Serial Overrun */
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+#define URX_OLD_DATA 0x1000 /* Old data in FIFO */
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+#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */
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+#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */
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+#define URX_FIFO_FULL 0x8000 /* FIFO is Full */
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+
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+/*
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+ * UART Transmitter Register
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+ */
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+#define UTX_ADDR 0xfffff906
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+#define UTX WORD_REF(UTX_ADDR)
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+
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+#define UTX_TXDATA_ADDR 0xfffff907
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+#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR)
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+
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+#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */
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+#define UTX_TXDATA_SHIFT 0
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+#define UTX_CTS_DELTA 0x0100 /* CTS changed */
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+#define UTX_CTS_STAT 0x0200 /* CTS State */
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+#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */
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+#define UTX_NOCTS 0x0800 /* Ignore CTS */
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+#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */
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+#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */
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+#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */
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+#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */
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+
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+/* '328-compatible definitions */
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+#define UTX_CTS_STATUS UTX_CTS_STAT
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+#define UTX_IGNORE_CTS UTX_NOCTS
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+
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+/*
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+ * UART Miscellaneous Register
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+ */
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+#define UMISC_ADDR 0xfffff908
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+#define UMISC WORD_REF(UMISC_ADDR)
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+
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+#define UMISC_TX_POL 0x0004 /* Transmit Polarity */
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+#define UMISC_RX_POL 0x0008 /* Receive Polarity */
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+#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */
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+#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */
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+#define UMISC_RTS 0x0040 /* Set RTS status */
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+#define UMISC_RTSCONT 0x0080 /* Choose RTS control */
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+#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */
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