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															+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c 
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															+ * 
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															+ * Copyright (c) 2007 Simtec Electronics 
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															+ * Copyright (c) 2007, 2008 Ben Dooks 
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															+ *	Ben Dooks <ben-linux@fluff.org> 
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															+ * 
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															+ * This program is free software; you can redistribute it and/or modify 
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															+ * it under the terms of the GNU General Public License as published by 
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															+ * the Free Software Foundation; either version 2 of the License. 
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															+*/ 
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															+#include <linux/init.h> 
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															+#include <linux/module.h> 
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															+#include <linux/kernel.h> 
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															+#include <linux/list.h> 
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															+#include <linux/errno.h> 
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															+#include <linux/log2.h> 
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															+#include <linux/clk.h> 
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															+#include <linux/err.h> 
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															+#include <linux/io.h> 
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															+#include <mach/hardware.h> 
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															+#include <mach/map.h> 
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															+#include <asm/irq.h> 
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															+#include <plat/clock.h> 
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															+#include <plat/cpu.h> 
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															+ 
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															+#include <plat/regs-timer.h> 
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															+#include <plat/pwm-clock.h> 
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															+ 
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															+/* Each of the timers 0 through 5 go through the following 
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															+ * clock tree, with the inputs depending on the timers. 
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															+ * 
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															+ * pclk ---- [ prescaler 0 ] -+---> timer 0 
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															+ *			      +---> timer 1 
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															+ * 
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															+ * pclk ---- [ prescaler 1 ] -+---> timer 2 
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															+ *			      +---> timer 3 
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															+ *			      \---> timer 4 
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															+ * 
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															+ * Which are fed into the timers as so: 
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															+ * 
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															+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\ 
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															+ *				       [mux] -> timer 0 
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															+ * tclk 0 ------------------------------/ 
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															+ * 
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															+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\ 
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															+ *				       [mux] -> timer 1 
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															+ * tclk 0 ------------------------------/ 
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															+ * 
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															+ * 
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															+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\ 
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															+ *				       [mux] -> timer 2 
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															+ * tclk 1 ------------------------------/ 
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															+ * 
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															+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\ 
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															+ *				       [mux] -> timer 3 
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															+ * tclk 1 ------------------------------/ 
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															+ * 
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															+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\ 
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															+ *				       [mux] -> timer 4 
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															+ * tclk 1 ------------------------------/ 
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															+ * 
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															+ * Since the mux and the divider are tied together in the 
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															+ * same register space, it is impossible to set the parent 
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															+ * and the rate at the same time. To avoid this, we add an 
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