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@@ -584,3 +584,50 @@ int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
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void omap1_clk_disable_unused(struct clk *clk)
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{
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__u32 regval32;
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+
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+ /* Clocks in the DSP domain need api_ck. Just assume bootloader
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+ * has not enabled any DSP clocks */
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+ if (clk->enable_reg == DSP_IDLECT2) {
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+ pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
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+ clk->name);
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+ return;
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+ }
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+
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+ /* Is the clock already disabled? */
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+ if (clk->flags & ENABLE_REG_32BIT)
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+ regval32 = __raw_readl(clk->enable_reg);
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+ else
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+ regval32 = __raw_readw(clk->enable_reg);
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+
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+ if ((regval32 & (1 << clk->enable_bit)) == 0)
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+ return;
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+
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+ printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
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+ clk->ops->disable(clk);
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+ printk(" done\n");
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+}
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+
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+#endif
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+
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+
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+int clk_enable(struct clk *clk)
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+{
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+ unsigned long flags;
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+ int ret;
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+
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+ if (clk == NULL || IS_ERR(clk))
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+ return -EINVAL;
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+
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+ spin_lock_irqsave(&clockfw_lock, flags);
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+ ret = omap1_clk_enable(clk);
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+ spin_unlock_irqrestore(&clockfw_lock, flags);
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+
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+ return ret;
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+}
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+EXPORT_SYMBOL(clk_enable);
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+
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+void clk_disable(struct clk *clk)
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+{
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+ unsigned long flags;
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+
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+ if (clk == NULL || IS_ERR(clk))
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