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+/*
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+ * sh73a0 clock framework support
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+ *
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+ * Copyright (C) 2010 Magnus Damm
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/sh_clk.h>
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+#include <linux/clkdev.h>
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+#include <mach/common.h>
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+
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+#define FRQCRA IOMEM(0xe6150000)
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+#define FRQCRB IOMEM(0xe6150004)
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+#define FRQCRD IOMEM(0xe61500e4)
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+#define VCLKCR1 IOMEM(0xe6150008)
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+#define VCLKCR2 IOMEM(0xe615000C)
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+#define VCLKCR3 IOMEM(0xe615001C)
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+#define ZBCKCR IOMEM(0xe6150010)
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+#define FLCKCR IOMEM(0xe6150014)
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+#define SD0CKCR IOMEM(0xe6150074)
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+#define SD1CKCR IOMEM(0xe6150078)
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+#define SD2CKCR IOMEM(0xe615007C)
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+#define FSIACKCR IOMEM(0xe6150018)
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+#define FSIBCKCR IOMEM(0xe6150090)
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+#define SUBCKCR IOMEM(0xe6150080)
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+#define SPUACKCR IOMEM(0xe6150084)
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+#define SPUVCKCR IOMEM(0xe6150094)
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+#define MSUCKCR IOMEM(0xe6150088)
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+#define HSICKCR IOMEM(0xe615008C)
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+#define MFCK1CR IOMEM(0xe6150098)
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+#define MFCK2CR IOMEM(0xe615009C)
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+#define DSITCKCR IOMEM(0xe6150060)
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+#define DSI0PCKCR IOMEM(0xe6150064)
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+#define DSI1PCKCR IOMEM(0xe6150068)
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+#define DSI0PHYCR 0xe615006C
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+#define DSI1PHYCR 0xe6150070
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+#define PLLECR IOMEM(0xe61500d0)
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+#define PLL0CR IOMEM(0xe61500d8)
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+#define PLL1CR IOMEM(0xe6150028)
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+#define PLL2CR IOMEM(0xe615002c)
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+#define PLL3CR IOMEM(0xe61500dc)
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+#define SMSTPCR0 IOMEM(0xe6150130)
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+#define SMSTPCR1 IOMEM(0xe6150134)
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+#define SMSTPCR2 IOMEM(0xe6150138)
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+#define SMSTPCR3 IOMEM(0xe615013c)
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+#define SMSTPCR4 IOMEM(0xe6150140)
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+#define SMSTPCR5 IOMEM(0xe6150144)
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+#define CKSCR IOMEM(0xe61500c0)
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+
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+/* Fixed 32 KHz root clock from EXTALR pin */
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+static struct clk r_clk = {
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+ .rate = 32768,
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+};
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+
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+/*
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+ * 26MHz default rate for the EXTAL1 root input clock.
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+ * If needed, reset this with clk_set_rate() from the platform code.
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+ */
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+struct clk sh73a0_extal1_clk = {
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+ .rate = 26000000,
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+};
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+
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+/*
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+ * 48MHz default rate for the EXTAL2 root input clock.
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+ * If needed, reset this with clk_set_rate() from the platform code.
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+ */
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+struct clk sh73a0_extal2_clk = {
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+ .rate = 48000000,
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+};
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+
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+/* A fixed divide-by-2 block */
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+static unsigned long div2_recalc(struct clk *clk)
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+{
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+ return clk->parent->rate / 2;
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+}
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+
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+static struct sh_clk_ops div2_clk_ops = {
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+ .recalc = div2_recalc,
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+};
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+
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+static unsigned long div7_recalc(struct clk *clk)
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+{
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+ return clk->parent->rate / 7;
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+}
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+
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+static struct sh_clk_ops div7_clk_ops = {
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+ .recalc = div7_recalc,
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+};
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+
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+static unsigned long div13_recalc(struct clk *clk)
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