|
@@ -202,3 +202,66 @@ static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
|
|
|
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
|
|
#define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
|
|
|
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
|
|
#define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
|
|
|
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
|
|
#define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
|
|
|
|
|
+#define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
|
|
|
|
|
+/* Source bus size */
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
|
|
|
|
|
+/* Source address increment */
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
|
|
|
|
|
+#define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
|
|
|
|
|
+/* Destination Bus Size */
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
|
|
|
|
|
+/* Destination address increment */
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
|
|
|
|
|
+#define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
|
|
|
|
|
+/* Master Mode (Master2 is only connected to MSL) */
|
|
|
|
|
+#define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
|
|
|
|
|
+#define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
|
|
|
|
|
+#define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
|
|
|
|
|
+#define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
|
|
|
|
|
+#define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
|
|
|
|
|
+/* Terminal Count flag to PER enable */
|
|
|
|
|
+#define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
|
|
|
|
|
+/* Terminal Count flags to CPU enable */
|
|
|
|
|
+#define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
|
|
|
|
|
+/* Hand shake to peripheral */
|
|
|
|
|
+#define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
|
|
|
|
|
+/* DMA mode */
|
|
|
|
|
+#define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
|
|
|
|
|
+#define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
|
|
|
|
|
+#define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
|
|
|
|
|
+/* Primary Request Data Destination */
|
|
|
|
|
+#define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
|
|
|
|
|
+#define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
|
|
|
|
|
+#define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
|
|
|
|
|
+ */
|
|
|
|
|
+#define COH901318_CX_SRC_ADDR (0x0404)
|
|
|
|
|
+#define COH901318_CX_SRC_ADDR_SPACING (0x10)
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
|
|
|
|
|
+ */
|
|
|
|
|
+#define COH901318_CX_DST_ADDR (0x0408)
|
|
|
|
|
+#define COH901318_CX_DST_ADDR_SPACING (0x10)
|
|
|
|
|
+
|
|
|
|
|
+/*
|
|
|
|
|
+ * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
|
|
|
|
|
+ */
|
|
|
|
|
+#define COH901318_CX_LNK_ADDR (0x040C)
|
|
|
|
|
+#define COH901318_CX_LNK_ADDR_SPACING (0x10)
|
|
|
|
|
+#define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
|
|
|
|
|
+#endif /* COH901318_H */
|
沈瑞清