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@@ -81,3 +81,145 @@ static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
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};
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static struct regulator_consumer_supply cm_t35_smsc911x_supplies[] = {
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+ REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
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+ REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
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+};
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+
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+static struct regulator_consumer_supply sb_t35_smsc911x_supplies[] = {
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+ REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
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+ REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
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+};
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+
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+static void __init cm_t35_init_ethernet(void)
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+{
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+ regulator_register_fixed(0, cm_t35_smsc911x_supplies,
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+ ARRAY_SIZE(cm_t35_smsc911x_supplies));
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+ regulator_register_fixed(1, sb_t35_smsc911x_supplies,
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+ ARRAY_SIZE(sb_t35_smsc911x_supplies));
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+
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+ gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
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+ gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
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+}
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+#else
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+static inline void __init cm_t35_init_ethernet(void) { return; }
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+#endif
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+
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+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
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+#include <linux/leds.h>
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+
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+static struct gpio_led cm_t35_leds[] = {
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+ [0] = {
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+ .gpio = 186,
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+ .name = "cm-t35:green",
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+ .default_trigger = "heartbeat",
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+ .active_low = 0,
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+ },
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+};
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+
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+static struct gpio_led_platform_data cm_t35_led_pdata = {
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+ .num_leds = ARRAY_SIZE(cm_t35_leds),
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+ .leds = cm_t35_leds,
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+};
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+
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+static struct platform_device cm_t35_led_device = {
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+ .name = "leds-gpio",
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+ .id = -1,
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+ .dev = {
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+ .platform_data = &cm_t35_led_pdata,
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+ },
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+};
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+
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+static void __init cm_t35_init_led(void)
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+{
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+ platform_device_register(&cm_t35_led_device);
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+}
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+#else
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+static inline void cm_t35_init_led(void) {}
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+#endif
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+
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+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/nand.h>
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+#include <linux/mtd/partitions.h>
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+
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+static struct mtd_partition cm_t35_nand_partitions[] = {
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+ {
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+ .name = "xloader",
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+ .offset = 0, /* Offset = 0x00000 */
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+ .size = 4 * NAND_BLOCK_SIZE,
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+ .mask_flags = MTD_WRITEABLE
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+ },
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+ {
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+ .name = "uboot",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
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+ .size = 15 * NAND_BLOCK_SIZE,
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+ },
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+ {
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+ .name = "uboot environment",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
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+ .size = 2 * NAND_BLOCK_SIZE,
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+ },
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+ {
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+ .name = "linux",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
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+ .size = 32 * NAND_BLOCK_SIZE,
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+ },
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+ {
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+ .name = "rootfs",
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+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
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+ .size = MTDPART_SIZ_FULL,
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+ },
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+};
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+
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+static struct omap_nand_platform_data cm_t35_nand_data = {
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+ .parts = cm_t35_nand_partitions,
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+ .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
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+ .cs = 0,
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+};
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+
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+static void __init cm_t35_init_nand(void)
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+{
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+ if (gpmc_nand_init(&cm_t35_nand_data, NULL) < 0)
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+ pr_err("CM-T35: Unable to register NAND device\n");
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+}
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+#else
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+static inline void cm_t35_init_nand(void) {}
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+#endif
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+
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+#define CM_T35_LCD_EN_GPIO 157
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+#define CM_T35_LCD_BL_GPIO 58
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+#define CM_T35_DVI_EN_GPIO 54
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+
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+static int lcd_enabled;
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+static int dvi_enabled;
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+
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+static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
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+{
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+ if (dvi_enabled) {
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+ printk(KERN_ERR "cannot enable LCD, DVI is enabled\n");
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+ return -EINVAL;
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+ }
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+
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+ gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
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+ gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
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+
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+ lcd_enabled = 1;
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+
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+ return 0;
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+}
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+
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+static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
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+{
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+ lcd_enabled = 0;
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+
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+ gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
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+ gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
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+}
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+
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+static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev)
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+{
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+ return 0;
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+}
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+
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+static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev)
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+{
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