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@@ -404,3 +404,126 @@
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#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
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#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1,val)
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#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
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+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2,val)
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+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
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+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0,val)
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+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
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+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1,val)
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+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
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+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2,val)
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+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
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+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3,val)
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+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
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+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0,val)
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+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
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+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1,val)
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+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
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+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2,val)
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+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
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+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
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+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
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+#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
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+#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1,val)
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+#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
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+#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2,val)
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+#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
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+#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV,val)
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+#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
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+#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV,val)
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+#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
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+#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
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+#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX,val)
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+#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX)
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+#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX)
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+#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX,val)
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+#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX)
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+#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX,val)
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+#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX)
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+#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX,val)
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+#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
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+#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1,val)
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+#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
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+#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2,val)
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+#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
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+#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV,val)
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+#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
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+#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV,val)
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+#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
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+#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT,val)
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+#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
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+#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL,val)
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+#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
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+#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1,val)
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+#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
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+#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2,val)
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+#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
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+#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0,val)
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+#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
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+#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1,val)
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+#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
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+#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2,val)
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+#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
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+#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3,val)
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+#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
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+#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0,val)
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+#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
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+#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1,val)
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+#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
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+#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2,val)
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+#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
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+#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3,val)
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+/* Asynchronous Memory Controller - External Bus Interface Unit */
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+#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
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+#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL,val)
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+#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
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+#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0,val)
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+#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
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+#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
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+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
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+#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
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+#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL,val)
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+#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL)
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+#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL,val)
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+#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
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+#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
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+#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
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+#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
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+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
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+#define bfin_read_PPI0_CONTROL() bfin_read16(PPI0_CONTROL)
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+#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
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+#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
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+#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
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+#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
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+#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
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+#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
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+#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
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+#define bfin_write_PPI0_DELAY(val) bfin_write16(PPI0_DELAY,val)
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+#define bfin_read_PPI0_FRAME() bfin_read16(PPI0_FRAME)
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+#define bfin_write_PPI0_FRAME(val) bfin_write16(PPI0_FRAME,val)
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+/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
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+#define bfin_read_PPI1_CONTROL() bfin_read16(PPI1_CONTROL)
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+#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
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+#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
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+#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
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+#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
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+#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
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+#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
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+#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)
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+#define bfin_write_PPI1_DELAY(val) bfin_write16(PPI1_DELAY,val)
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+#define bfin_read_PPI1_FRAME() bfin_read16(PPI1_FRAME)
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+#define bfin_write_PPI1_FRAME(val) bfin_write16(PPI1_FRAME,val)
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+/*DMA traffic control registers */
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+#define bfin_read_DMAC0_TC_PER() bfin_read16(DMAC0_TC_PER)
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+#define bfin_write_DMAC0_TC_PER(val) bfin_write16(DMAC0_TC_PER,val)
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+#define bfin_read_DMAC0_TC_CNT() bfin_read16(DMAC0_TC_CNT)
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+#define bfin_write_DMAC0_TC_CNT(val) bfin_write16(DMAC0_TC_CNT,val)
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+#define bfin_read_DMAC1_TC_PER() bfin_read16(DMAC1_TC_PER)
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+#define bfin_write_DMAC1_TC_PER(val) bfin_write16(DMAC1_TC_PER,val)
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+#define bfin_read_DMAC1_TC_CNT() bfin_read16(DMAC1_TC_CNT)
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+#define bfin_write_DMAC1_TC_CNT(val) bfin_write16(DMAC1_TC_CNT,val)
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+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
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+#define bfin_read_DMA1_0_CONFIG() bfin_read16(DMA1_0_CONFIG)
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+#define bfin_write_DMA1_0_CONFIG(val) bfin_write16(DMA1_0_CONFIG,val)
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+#define bfin_read_DMA1_0_NEXT_DESC_PTR() bfin_read32(DMA1_0_NEXT_DESC_PTR)
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