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@@ -165,3 +165,117 @@
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#define RE 0x00000001 /* Receiver Enable */
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#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
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#define HU 0x00000010 /* Hash Filter Unicast Address */
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+#define HM 0x00000020 /* Hash Filter Multicast Address */
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+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
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+#define PR 0x00000080 /* Promiscuous Mode Enable */
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+#define IFE 0x00000100 /* Inverse Filtering Enable */
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+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
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+#define PBF 0x00000400 /* Pass Bad Frames Enable */
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+#define PSF 0x00000800 /* Pass Short Frames Enable */
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+#define RAF 0x00001000 /* Receive-All Mode */
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+#define TE 0x00010000 /* Transmitter Enable */
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+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
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+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
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+#define DC 0x00080000 /* Deferral Check */
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+#define BOLMT 0x00300000 /* Back-Off Limit */
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+#define BOLMT_10 0x00000000 /* 10-bit range */
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+#define BOLMT_8 0x00100000 /* 8-bit range */
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+#define BOLMT_4 0x00200000 /* 4-bit range */
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+#define BOLMT_1 0x00300000 /* 1-bit range */
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+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
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+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
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+#define RMII 0x01000000 /* RMII/MII* Mode */
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+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
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+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
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+#define LB 0x08000000 /* Internal Loopback Enable */
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+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
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+
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+/* EMAC_STAADD Masks */
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+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
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+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
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+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
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+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
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+#define REGAD 0x000007C0 /* STA Register Address */
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+#define PHYAD 0x0000F800 /* PHY Device Address */
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+
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+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
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+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
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+
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+/* EMAC_STADAT Mask */
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+#define STADATA 0x0000FFFF /* Station Management Data */
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+
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+/* EMAC_FLC Masks */
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+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
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+#define FLCE 0x00000002 /* Flow Control Enable */
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+#define PCF 0x00000004 /* Pass Control Frames */
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+#define BKPRSEN 0x00000008 /* Enable Backpressure */
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+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
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+
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+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
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+
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+/* EMAC_WKUP_CTL Masks */
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+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
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+#define MPKE 0x00000002 /* Magic Packet Enable */
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+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
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+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
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+#define MPKS 0x00000020 /* Magic Packet Received Status */
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+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
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+
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+/* EMAC_WKUP_FFCMD Masks */
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+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
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+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
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+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
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+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
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+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
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+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
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+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
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+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
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+
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+/* EMAC_WKUP_FFOFF Masks */
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+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
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+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
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+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
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+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
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+
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+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
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+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
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+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
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+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
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+/* Set ALL Offsets */
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+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
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+
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+/* EMAC_WKUP_FFCRC0 Masks */
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+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
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+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
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+
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+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
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+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
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+
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+/* EMAC_WKUP_FFCRC1 Masks */
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+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
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+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
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+
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+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
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+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
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+
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+/* EMAC_SYSCTL Masks */
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+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
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+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
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+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
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+#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
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+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
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+
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+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
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+
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+/* EMAC_SYSTAT Masks */
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+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
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+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
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+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
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+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
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+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
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+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
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+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
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+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
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+
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+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
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+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
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