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@@ -103,3 +103,72 @@
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#define DMA1_CMD_REG 0x08 /* command register (w) */
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#define DMA1_STAT_REG 0x08 /* status register (r) */
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#define DMA1_REQ_REG 0x09 /* request register (w) */
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+#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
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+#define DMA1_MODE_REG 0x0B /* mode register (w) */
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+#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
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+#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
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+#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
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+#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
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+#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
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+
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+#define DMA2_CMD_REG 0xD0 /* command register (w) */
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+#define DMA2_STAT_REG 0xD0 /* status register (r) */
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+#define DMA2_REQ_REG 0xD2 /* request register (w) */
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+#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
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+#define DMA2_MODE_REG 0xD6 /* mode register (w) */
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+#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
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+#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
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+#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
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+#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
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+#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
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+
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+#define DMA_ADDR_0 0x00 /* DMA address registers */
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+#define DMA_ADDR_1 0x02
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+#define DMA_ADDR_2 0x04
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+#define DMA_ADDR_3 0x06
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+#define DMA_ADDR_4 0xC0
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+#define DMA_ADDR_5 0xC4
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+#define DMA_ADDR_6 0xC8
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+#define DMA_ADDR_7 0xCC
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+
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+#define DMA_CNT_0 0x01 /* DMA count registers */
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+#define DMA_CNT_1 0x03
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+#define DMA_CNT_2 0x05
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+#define DMA_CNT_3 0x07
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+#define DMA_CNT_4 0xC2
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+#define DMA_CNT_5 0xC6
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+#define DMA_CNT_6 0xCA
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+#define DMA_CNT_7 0xCE
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+
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+#define DMA_PAGE_0 0x87 /* DMA page registers */
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+#define DMA_PAGE_1 0x83
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+#define DMA_PAGE_2 0x81
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+#define DMA_PAGE_3 0x82
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+#define DMA_PAGE_5 0x8B
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+#define DMA_PAGE_6 0x89
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+#define DMA_PAGE_7 0x8A
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+
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+#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
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+#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
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+#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
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+
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+#define DMA_AUTOINIT 0x10
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+
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+extern spinlock_t dma_spin_lock;
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+
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+static __inline__ unsigned long claim_dma_lock(void)
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+{
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+ unsigned long flags;
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+ spin_lock_irqsave(&dma_spin_lock, flags);
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+ return flags;
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+}
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+
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+static __inline__ void release_dma_lock(unsigned long flags)
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+{
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+ spin_unlock_irqrestore(&dma_spin_lock, flags);
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+}
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+
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+/* enable/disable a specific DMA channel */
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+static __inline__ void enable_dma(unsigned int dmanr)
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+{
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+ if (dmanr<=3)
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