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+/*
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+ * Copyright (C) 2009 Nokia
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+ * Copyright (C) 2009 Texas Instruments
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
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+
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+#define OMAP3_MUX(mode0, mux_value) \
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+{ \
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+ .reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
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+ .value = (mux_value), \
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+}
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+
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+/*
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+ * OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
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+ *
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+ * Extracted from the TRM. Add 0x48002030 to these values to get the
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+ * absolute addresses. The name in the macro is the mode-0 name of
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+ * the pin. NOTE: These registers are 16-bits wide.
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+ *
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+ * Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
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+ * of CHASSIS for some registers. For the defines, we follow the
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+ * 36XX naming, and use SDMMC and CHASSIS.
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+ */
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+#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
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+#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
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+#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
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+#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
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+#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
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+#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
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+#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
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+#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
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+#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
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+#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
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+#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
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+#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
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+#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
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+#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
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+#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
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+#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
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+#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
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+#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
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+#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
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+#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
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+#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
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+#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
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+#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
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+#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
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+#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
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+#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
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+#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
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+#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
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+#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
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+#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
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+#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
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+#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
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+#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
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+#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
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+#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
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+#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
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+#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
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+#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
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+#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
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+#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
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+#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
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+#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
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+#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
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+#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
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+#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
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+#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
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+#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
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+#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
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+#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
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+#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
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+#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
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+#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
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+#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
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+#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
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+#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
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+#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
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+#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
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+#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
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+#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
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+#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
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+#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
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+#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
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+#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
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+#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
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+#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
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+#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
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+#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
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+#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
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+#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
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+#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
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+#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
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+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
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+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
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+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
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+#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
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+#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
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+#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
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+#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
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+#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
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+#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
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+#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
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+#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
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+#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
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+#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
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+#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
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+#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
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+#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
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+#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
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+#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
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+#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
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+#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
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+#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
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+#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
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+#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
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+#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
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+#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
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+#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
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+#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
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+#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
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+#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
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+#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
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+#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
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+#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
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+#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
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+#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
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唐峰