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				@@ -505,3 +505,94 @@ 
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				 #define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */ 
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				+/* Bit masks for PIXC_AHEND */ 
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				+#define                    A_HEND  0xfff      /* Horizontal End Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_AVSTART */ 
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				+#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_AVEND */ 
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				+ 
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				+#define                    A_VEND  0x3ff      /* Vertical End Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_ATRANSP */ 
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				+#define                  A_TRANSP  0xf        /* Transparency Value */ 
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				+ 
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				+/* Bit masks for PIXC_BHSTART */ 
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				+ 
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				+#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_BHEND */ 
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				+ 
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				+#define                    B_HEND  0xfff      /* Horizontal End Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_BVSTART */ 
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				+ 
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				+#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_BVEND */ 
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				+ 
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				+#define                    B_VEND  0x3ff      /* Vertical End Coordinates */ 
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				+ 
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				+/* Bit masks for PIXC_BTRANSP */ 
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				+ 
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				+#define                  B_TRANSP  0xf        /* Transparency Value */ 
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				+ 
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				+/* Bit masks for PIXC_INTRSTAT */ 
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				+#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */ 
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				+#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */ 
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				+#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */ 
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				+#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */ 
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				+ 
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				+/* Bit masks for PIXC_RYCON */ 
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				+#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */ 
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				+#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */ 
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				+#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */ 
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				+#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */ 
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				+ 
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				+/* Bit masks for PIXC_GUCON */ 
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				+#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */ 
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				+#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */ 
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				+#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */ 
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				+#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */ 
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				+ 
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				+/* Bit masks for PIXC_BVCON */ 
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				+#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */ 
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				+#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */ 
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				+#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */ 
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				+#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */ 
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				+ 
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				+/* Bit masks for PIXC_CCBIAS */ 
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				+ 
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				+#define                       A14  0x3ff      /* A14 in the Bias Vector */ 
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				+#define                       A24  0xffc00    /* A24 in the Bias Vector */ 
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				+#define                       A34  0x3ff00000 /* A34 in the Bias Vector */ 
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				+ 
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				+/* Bit masks for PIXC_TC */ 
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				+ 
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				+#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */ 
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				+#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */ 
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				+#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */ 
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				+ 
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				+/* Bit masks for HOST_CONTROL */ 
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				+ 
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				+#define                   HOST_EN  0x1        /* Host Enable */ 
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				+#define                  HOST_END  0x2        /* Host Endianess */ 
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				+#define                 DATA_SIZE  0x4        /* Data Size */ 
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				+#define                  HOST_RST  0x8        /* Host Reset */ 
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				+#define                  HRDY_OVR  0x20       /* Host Ready Override */ 
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				+#define                  INT_MODE  0x40       /* Interrupt Mode */ 
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				+#define                     BT_EN  0x80       /* Bus Timeout Enable */ 
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				+#define                       EHW  0x100      /* Enable Host Write */ 
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				+#define                       EHR  0x200      /* Enable Host Read */ 
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				+#define                       BDR  0x400      /* Burst DMA Requests */ 
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				+ 
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				+/* Bit masks for HOST_STATUS */ 
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				+ 
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