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@@ -405,3 +405,188 @@
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#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
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#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
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#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
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+#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
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+#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
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+#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
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+#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
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+#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
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+#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
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+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
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+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
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+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
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+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
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+
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+/* Chip ID register 16bit (R/-) */
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+#define U300_SYSCON_CIDR (0x400)
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+/* Video IRQ clear 16bit (R/W) */
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+#define U300_SYSCON_VICR (0x404)
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+#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
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+#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
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+/* SMCR */
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+#define U300_SYSCON_SMCR (0x4d0)
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+#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
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+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
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+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
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+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
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+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
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+#define U300_SYSCON_CSDR (0x4f0)
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+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
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+/* PRINT_CONTROL Print Control 16bit (R/-) */
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+#define U300_SYSCON_PCR (0x4f8)
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+#define U300_SYSCON_PCR_SERV_IND (0x0001)
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+/* BOOT_CONTROL 16bit (R/-) */
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+#define U300_SYSCON_BCR (0x4fc)
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+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
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+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
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+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
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+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
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+
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+
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+/* CPU clock defines */
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+/**
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+ * CPU high frequency in MHz
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+ */
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+#define SYSCON_CPU_CLOCK_HIGH 208
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+/**
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+ * CPU medium frequency in MHz
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+ */
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+#define SYSCON_CPU_CLOCK_MEDIUM 52
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+/**
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+ * CPU low frequency in MHz
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+ */
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+#define SYSCON_CPU_CLOCK_LOW 13
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+
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+/* EMIF clock defines */
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+/**
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+ * EMIF high frequency in MHz
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+ */
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+#define SYSCON_EMIF_CLOCK_HIGH 104
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+/**
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+ * EMIF medium frequency in MHz
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+ */
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+#define SYSCON_EMIF_CLOCK_MEDIUM 52
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+/**
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+ * EMIF low frequency in MHz
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+ */
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+#define SYSCON_EMIF_CLOCK_LOW 13
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+
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+/* AHB clock defines */
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+/**
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+ * AHB high frequency in MHz
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+ */
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+#define SYSCON_AHB_CLOCK_HIGH 52
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+/**
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+ * AHB medium frequency in MHz
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+ */
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+#define SYSCON_AHB_CLOCK_MEDIUM 26
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+/**
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+ * AHB low frequency in MHz
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+ */
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+#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
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+
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+enum syscon_busmaster {
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+ SYSCON_BM_DMAC,
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+ SYSCON_BM_XGAM,
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+ SYSCON_BM_VIDEO_ENC
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+};
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+
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+/* Selectr a resistor or a set of resistors */
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+enum syscon_pull_up_down {
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+ SYSCON_PU_KEY_IN_EN,
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+ SYSCON_PU_EMIF_1_8_BIT_EN,
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+ SYSCON_PU_EMIF_1_16_BIT_EN,
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+ SYSCON_PU_EMIF_1_NFIF_READY_EN,
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+ SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
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+};
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+
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+/*
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+ * Note that this array must match the order of the array "clk_reg"
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+ * in syscon.c
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+ */
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+enum syscon_clk {
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+ SYSCON_CLKCONTROL_SLOW_BRIDGE,
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+ SYSCON_CLKCONTROL_UART,
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+ SYSCON_CLKCONTROL_BTR,
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+ SYSCON_CLKCONTROL_EH,
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+ SYSCON_CLKCONTROL_GPIO,
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+ SYSCON_CLKCONTROL_KEYPAD,
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+ SYSCON_CLKCONTROL_APP_TIMER,
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+ SYSCON_CLKCONTROL_ACC_TIMER,
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+ SYSCON_CLKCONTROL_FAST_BRIDGE,
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+ SYSCON_CLKCONTROL_I2C0,
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+ SYSCON_CLKCONTROL_I2C1,
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+ SYSCON_CLKCONTROL_I2S0,
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+ SYSCON_CLKCONTROL_I2S1,
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+ SYSCON_CLKCONTROL_MMC,
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+ SYSCON_CLKCONTROL_SPI,
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+ SYSCON_CLKCONTROL_I2S0_CORE,
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+ SYSCON_CLKCONTROL_I2S1_CORE,
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+ SYSCON_CLKCONTROL_UART1,
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+ SYSCON_CLKCONTROL_AAIF,
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+ SYSCON_CLKCONTROL_AHB,
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+ SYSCON_CLKCONTROL_APEX,
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+ SYSCON_CLKCONTROL_CPU,
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+ SYSCON_CLKCONTROL_DMA,
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+ SYSCON_CLKCONTROL_EMIF,
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+ SYSCON_CLKCONTROL_NAND_IF,
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+ SYSCON_CLKCONTROL_VIDEO_ENC,
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+ SYSCON_CLKCONTROL_XGAM,
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+ SYSCON_CLKCONTROL_SEMI,
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+ SYSCON_CLKCONTROL_AHB_SUBSYS,
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+ SYSCON_CLKCONTROL_MSPRO
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+};
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+
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+enum syscon_sysclk_mode {
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+ SYSCON_SYSCLK_DISABLED,
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+ SYSCON_SYSCLK_M_CLK,
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+ SYSCON_SYSCLK_ACC_FSM,
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+ SYSCON_SYSCLK_PLL60_48,
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+ SYSCON_SYSCLK_PLL60_60,
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+ SYSCON_SYSCLK_ACC_PLL208,
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+ SYSCON_SYSCLK_APP_PLL13,
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+ SYSCON_SYSCLK_APP_FSM,
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+ SYSCON_SYSCLK_RTC,
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+ SYSCON_SYSCLK_APP_PLL208
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+};
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+
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+enum syscon_sysclk_req {
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+ SYSCON_SYSCLKREQ_DISABLED,
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+ SYSCON_SYSCLKREQ_ACTIVE_LOW,
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+ SYSCON_SYSCLKREQ_MONITOR
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+};
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+
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+enum syscon_clk_mode {
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+ SYSCON_CLKMODE_OFF,
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+ SYSCON_CLKMODE_DEFAULT,
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+ SYSCON_CLKMODE_LOW,
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+ SYSCON_CLKMODE_MEDIUM,
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+ SYSCON_CLKMODE_HIGH,
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+ SYSCON_CLKMODE_PERMANENT,
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+ SYSCON_CLKMODE_ON,
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+};
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+
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+enum syscon_call_mode {
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+ SYSCON_CLKCALL_NOWAIT,
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+ SYSCON_CLKCALL_WAIT,
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+};
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+
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+int syscon_dc_on(bool keep_power_on);
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+int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
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+ bool active);
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+bool syscon_get_busmaster_active_state(void);
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+int syscon_set_sleep_mask(enum syscon_clk,
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+ bool sleep_ctrl);
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+int syscon_config_sysclk(u32 sysclk,
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+ enum syscon_sysclk_mode sysclkmode,
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+ bool inverse,
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+ u32 divisor,
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+ enum syscon_sysclk_req sysclkreq);
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+bool syscon_can_turn_off_semi_clock(void);
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+
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+/* This function is restricted to core.c */
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+int syscon_request_normal_power(bool req);
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+
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+/* This function is restricted to be used by platform_speed.c */
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+int syscon_speed_request(enum syscon_call_mode wait_mode,
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+ enum syscon_clk_mode req_clk_mode);
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+#endif /* __MACH_SYSCON_H */
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李欣儒