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@@ -342,3 +342,61 @@
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#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038
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#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
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#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c
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+#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
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+
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+/* CM.MPU_CM register offsets */
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+#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
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+#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
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+#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004
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+#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
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+
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+/* CM.DEVICE_CM register offsets */
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+#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000
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+#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
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+
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+/* CM.RTC_CM register offsets */
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+#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000
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+#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
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+#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004
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+#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
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+
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+/* CM.GFX_CM register offsets */
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+#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000
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+#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
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+#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004
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+#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
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+#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008
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+#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
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+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c
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+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
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+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010
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+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
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+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014
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+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
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+
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+/* CM.CEFUSE_CM register offsets */
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+#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000
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+#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
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+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
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+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
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+
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+
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+extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
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+extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
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+extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
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+extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
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+extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
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+
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+#ifdef CONFIG_SOC_AM33XX
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+extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs);
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+#else
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+static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
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+ u16 clkctrl_offs)
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+{
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