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@@ -596,3 +596,63 @@
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/* Bit masks for HOST_STATUS */
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+#define DMA_READY 0x1 /* DMA Ready */
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+#define FIFOFULL 0x2 /* FIFO Full */
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+#define FIFOEMPTY 0x4 /* FIFO Empty */
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+#define DMA_COMPLETE 0x8 /* DMA Complete */
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+#define HSHK 0x10 /* Host Handshake */
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+#define HSTIMEOUT 0x20 /* Host Timeout */
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+#define HIRQ 0x40 /* Host Interrupt Request */
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+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
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+#define DMA_DIR 0x100 /* DMA Direction */
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+#define BTE 0x200 /* Bus Timeout Enabled */
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+
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+/* Bit masks for HOST_TIMEOUT */
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+
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+#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
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+
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+/* Bit masks for KPAD_CTL */
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+
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+#define KPAD_EN 0x1 /* Keypad Enable */
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+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
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+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
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+#define KPAD_COLEN 0xe000 /* Column Enable Width */
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+
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+/* Bit masks for KPAD_PRESCALE */
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+
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+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
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+
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+/* Bit masks for KPAD_MSEL */
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+
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+#define DBON_SCALE 0xff /* Debounce Scale Value */
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+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
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+
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+/* Bit masks for KPAD_ROWCOL */
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+
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+#define KPAD_ROW 0xff /* Rows Pressed */
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+#define KPAD_COL 0xff00 /* Columns Pressed */
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+
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+/* Bit masks for KPAD_STAT */
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+
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+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
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+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
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+#define KPAD_PRESSED 0x8 /* Key press current status */
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+
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+/* Bit masks for KPAD_SOFTEVAL */
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+
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+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
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+
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+/* Bit masks for ATAPI_CONTROL */
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+
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+#define PIO_START 0x1 /* Start PIO/Reg Op */
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+#define MULTI_START 0x2 /* Start Multi-DMA Op */
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+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
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+#define XFER_DIR 0x8 /* Transfer Direction */
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+#define IORDY_EN 0x10 /* IORDY Enable */
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+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
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+#define SOFT_RST 0x40 /* Soft Reset */
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+#define DEV_RST 0x80 /* Device Reset */
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+#define TFRCNT_RST 0x100 /* Trans Count Reset */
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+#define END_ON_TERM 0x200 /* End/Terminate Select */
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+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
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+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
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