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@@ -371,3 +371,181 @@
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B0 = I0;
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B0 = I0;
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B1 = I0;
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B1 = I0;
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B2 = I0;
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B2 = I0;
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+ B3 = I0;
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+ I1.L = lo(DCPLB_ADDR0);
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+ I2.L = lo(DCPLB_DATA0);
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+ I3.L = lo(ICPLB_ADDR0);
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+ B0.L = lo(ICPLB_DATA0);
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+ B1.L = lo(EVT2);
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+ B2.L = lo(IMASK);
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+ B3.L = lo(TCNTL);
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+
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+ /* Event Vectors */
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+ FP = B1;
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+ PM_PUSH(0, EVT2)
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+ PM_PUSH(1, EVT3)
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+ FP += 4; /* EVT4 */
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+ PM_PUSH(2, EVT5)
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+ PM_PUSH(3, EVT6)
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+ PM_PUSH(4, EVT7)
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+ PM_PUSH(5, EVT8)
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+ PM_PUSH_SYNC(5)
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+
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+ PM_PUSH(0, EVT9)
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+ PM_PUSH(1, EVT10)
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+ PM_PUSH(2, EVT11)
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+ PM_PUSH(3, EVT12)
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+ PM_PUSH(4, EVT13)
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+ PM_PUSH(5, EVT14)
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+ PM_PUSH(6, EVT15)
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+
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+ /* CEC */
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+ FP = B2;
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+ PM_PUSH(7, IMASK)
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+ FP += 4; /* IPEND */
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+ PM_PUSH(8, ILAT)
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+ PM_PUSH(9, IPRIO)
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+
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+ /* Core Timer */
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+ FP = B3;
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+ PM_PUSH(10, TCNTL)
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+ PM_PUSH(11, TPERIOD)
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+ PM_PUSH(12, TSCALE)
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+ PM_PUSH(13, TCOUNT)
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+ PM_PUSH_SYNC(13)
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+
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+ /* Misc non-contiguous registers */
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+ FP = I0;
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+ PM_CORE_PUSH(0, DMEM_CONTROL);
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+ PM_CORE_PUSH(1, IMEM_CONTROL);
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+ PM_CORE_PUSH(2, TBUFCTL);
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+ PM_PUSH_SYNC(2)
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+
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+ /* DCPLB Addr */
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+ FP = I1;
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+ PM_PUSH(0, DCPLB_ADDR0)
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+ PM_PUSH(1, DCPLB_ADDR1)
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+ PM_PUSH(2, DCPLB_ADDR2)
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+ PM_PUSH(3, DCPLB_ADDR3)
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+ PM_PUSH(4, DCPLB_ADDR4)
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+ PM_PUSH(5, DCPLB_ADDR5)
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+ PM_PUSH(6, DCPLB_ADDR6)
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+ PM_PUSH(7, DCPLB_ADDR7)
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+ PM_PUSH(8, DCPLB_ADDR8)
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+ PM_PUSH(9, DCPLB_ADDR9)
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+ PM_PUSH(10, DCPLB_ADDR10)
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+ PM_PUSH(11, DCPLB_ADDR11)
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+ PM_PUSH(12, DCPLB_ADDR12)
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+ PM_PUSH(13, DCPLB_ADDR13)
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+ PM_PUSH_SYNC(13)
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+ PM_PUSH(0, DCPLB_ADDR14)
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+ PM_PUSH(1, DCPLB_ADDR15)
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+
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+ /* DCPLB Data */
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+ FP = I2;
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+ PM_PUSH(2, DCPLB_DATA0)
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+ PM_PUSH(3, DCPLB_DATA1)
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+ PM_PUSH(4, DCPLB_DATA2)
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+ PM_PUSH(5, DCPLB_DATA3)
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+ PM_PUSH(6, DCPLB_DATA4)
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+ PM_PUSH(7, DCPLB_DATA5)
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+ PM_PUSH(8, DCPLB_DATA6)
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+ PM_PUSH(9, DCPLB_DATA7)
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+ PM_PUSH(10, DCPLB_DATA8)
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+ PM_PUSH(11, DCPLB_DATA9)
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+ PM_PUSH(12, DCPLB_DATA10)
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+ PM_PUSH(13, DCPLB_DATA11)
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+ PM_PUSH_SYNC(13)
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+ PM_PUSH(0, DCPLB_DATA12)
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+ PM_PUSH(1, DCPLB_DATA13)
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+ PM_PUSH(2, DCPLB_DATA14)
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+ PM_PUSH(3, DCPLB_DATA15)
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+
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+ /* ICPLB Addr */
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+ FP = I3;
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+ PM_PUSH(4, ICPLB_ADDR0)
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+ PM_PUSH(5, ICPLB_ADDR1)
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+ PM_PUSH(6, ICPLB_ADDR2)
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+ PM_PUSH(7, ICPLB_ADDR3)
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+ PM_PUSH(8, ICPLB_ADDR4)
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+ PM_PUSH(9, ICPLB_ADDR5)
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+ PM_PUSH(10, ICPLB_ADDR6)
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+ PM_PUSH(11, ICPLB_ADDR7)
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+ PM_PUSH(12, ICPLB_ADDR8)
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+ PM_PUSH(13, ICPLB_ADDR9)
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+ PM_PUSH_SYNC(13)
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+ PM_PUSH(0, ICPLB_ADDR10)
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+ PM_PUSH(1, ICPLB_ADDR11)
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+ PM_PUSH(2, ICPLB_ADDR12)
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+ PM_PUSH(3, ICPLB_ADDR13)
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+ PM_PUSH(4, ICPLB_ADDR14)
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+ PM_PUSH(5, ICPLB_ADDR15)
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+
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+ /* ICPLB Data */
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+ FP = B0;
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+ PM_PUSH(6, ICPLB_DATA0)
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+ PM_PUSH(7, ICPLB_DATA1)
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+ PM_PUSH(8, ICPLB_DATA2)
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+ PM_PUSH(9, ICPLB_DATA3)
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+ PM_PUSH(10, ICPLB_DATA4)
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+ PM_PUSH(11, ICPLB_DATA5)
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+ PM_PUSH(12, ICPLB_DATA6)
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+ PM_PUSH(13, ICPLB_DATA7)
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+ PM_PUSH_SYNC(13)
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+ PM_PUSH(0, ICPLB_DATA8)
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+ PM_PUSH(1, ICPLB_DATA9)
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+ PM_PUSH(2, ICPLB_DATA10)
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+ PM_PUSH(3, ICPLB_DATA11)
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+ PM_PUSH(4, ICPLB_DATA12)
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+ PM_PUSH(5, ICPLB_DATA13)
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+ PM_PUSH(6, ICPLB_DATA14)
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+ PM_PUSH(7, ICPLB_DATA15)
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+ PM_PUSH_SYNC(7)
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+ .endm
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+
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+ .macro bfin_core_mmr_restore
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+ /* Restore Core MMRs */
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+ I0.H = hi(COREMMR_BASE);
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+ I0.L = lo(COREMMR_BASE);
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+ I1 = I0;
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+ I2 = I0;
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+ I3 = I0;
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+ B0 = I0;
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+ B1 = I0;
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+ B2 = I0;
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+ B3 = I0;
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+ I1.L = lo(DCPLB_ADDR15);
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+ I2.L = lo(DCPLB_DATA15);
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+ I3.L = lo(ICPLB_ADDR15);
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+ B0.L = lo(ICPLB_DATA15);
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+ B1.L = lo(EVT15);
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+ B2.L = lo(IPRIO);
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+ B3.L = lo(TCOUNT);
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+
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+ /* ICPLB Data */
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+ FP = B0;
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+ PM_POP_SYNC(7)
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+ PM_POP(7, ICPLB_DATA15)
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+ PM_POP(6, ICPLB_DATA14)
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+ PM_POP(5, ICPLB_DATA13)
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+ PM_POP(4, ICPLB_DATA12)
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+ PM_POP(3, ICPLB_DATA11)
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+ PM_POP(2, ICPLB_DATA10)
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+ PM_POP(1, ICPLB_DATA9)
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+ PM_POP(0, ICPLB_DATA8)
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+ PM_POP_SYNC(13)
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+ PM_POP(13, ICPLB_DATA7)
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+ PM_POP(12, ICPLB_DATA6)
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+ PM_POP(11, ICPLB_DATA5)
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+ PM_POP(10, ICPLB_DATA4)
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+ PM_POP(9, ICPLB_DATA3)
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+ PM_POP(8, ICPLB_DATA2)
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+ PM_POP(7, ICPLB_DATA1)
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+ PM_POP(6, ICPLB_DATA0)
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+
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+ /* ICPLB Addr */
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+ FP = I3;
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+ PM_POP(5, ICPLB_ADDR15)
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+ PM_POP(4, ICPLB_ADDR14)
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+ PM_POP(3, ICPLB_ADDR13)
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+ PM_POP(2, ICPLB_ADDR12)
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