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@@ -312,3 +312,97 @@ void omap1_pm_suspend(void)
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/* Stop all DSP domain clocks */
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__raw_writew(0, DSP_IDLECT2);
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+
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+ /*
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+ * Step 5: Wakeup Event Setup
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+ */
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+
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+ omap_pm_wakeup_setup();
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+
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+ /*
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+ * Step 6: ARM and Traffic controller shutdown
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+ */
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+
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+ /* disable ARM watchdog */
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+ omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
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+ omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
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+
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+ /*
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+ * Step 6b: ARM and Traffic controller shutdown
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+ *
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+ * Step 6 continues here. Prepare jump to power management
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+ * assembly code in internal SRAM.
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+ *
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+ * Since the omap_cpu_suspend routine has been copied to
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+ * SRAM, we'll do an indirect procedure call to it and pass the
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+ * contents of arm_idlect1 and arm_idlect2 so it can restore
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+ * them when it wakes up and it will return.
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+ */
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+
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+ arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
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+ arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
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+
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+ /*
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+ * Step 6c: ARM and Traffic controller shutdown
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+ *
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+ * Jump to assembly code. The processor will stay there
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+ * until wake up.
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+ */
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+ omap_sram_suspend(arg0, arg1);
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+
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+ /*
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+ * If we are here, processor is woken up!
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+ */
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+
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+ /*
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+ * Restore DSP clocks
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+ */
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+
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+ /* again temporarily enabling api_ck to access DSP registers */
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+ omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
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+
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+ /* Restore DSP domain clocks */
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+ DSP_RESTORE(DSP_IDLECT2);
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+
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+ /*
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+ * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
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+ */
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+
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+ if (!(cpu_is_omap15xx()))
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+ ARM_RESTORE(ARM_IDLECT3);
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+ ARM_RESTORE(ARM_CKCTL);
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+ ARM_RESTORE(ARM_EWUPCT);
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+ ARM_RESTORE(ARM_RSTCT1);
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+ ARM_RESTORE(ARM_RSTCT2);
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+ ARM_RESTORE(ARM_SYSST);
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+ ULPD_RESTORE(ULPD_CLOCK_CTRL);
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+ ULPD_RESTORE(ULPD_STATUS_REQ);
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+
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+ if (cpu_is_omap7xx()) {
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+ MPUI7XX_RESTORE(EMIFS_CONFIG);
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+ MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
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+ MPUI7XX_RESTORE(OMAP_IH1_MIR);
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+ MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
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+ MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
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+ } else if (cpu_is_omap15xx()) {
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+ MPUI1510_RESTORE(MPUI_CTRL);
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+ MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
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+ MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
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+ MPUI1510_RESTORE(EMIFS_CONFIG);
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+ MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
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+ MPUI1510_RESTORE(OMAP_IH1_MIR);
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+ MPUI1510_RESTORE(OMAP_IH2_MIR);
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+ } else if (cpu_is_omap16xx()) {
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+ MPUI1610_RESTORE(MPUI_CTRL);
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+ MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
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+ MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
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+ MPUI1610_RESTORE(EMIFS_CONFIG);
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+ MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
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+
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+ MPUI1610_RESTORE(OMAP_IH1_MIR);
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+ MPUI1610_RESTORE(OMAP_IH2_0_MIR);
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+ MPUI1610_RESTORE(OMAP_IH2_1_MIR);
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+ MPUI1610_RESTORE(OMAP_IH2_2_MIR);
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+ MPUI1610_RESTORE(OMAP_IH2_3_MIR);
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+ }
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+
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王祥