efHotAgingTrendMining influenceAnalysisOfCableAging.h 朱涛 commit at 2020-12-02

efHotAgingTrendMining/thermalAnalysisOfCable/influenceAnalysisOfCableAging.h

@@ -567,3 +567,89 @@
 #define OMAP4_MCSPI1_DR0_SC_MASK				(0x3 << 10)
 #define OMAP4_UART1_DR0_SC_SHIFT				8
 #define OMAP4_UART1_DR0_SC_MASK					(0x3 << 8)
+#define OMAP4_UART3_DR0_SC_SHIFT				6
+#define OMAP4_UART3_DR0_SC_MASK					(0x3 << 6)
+#define OMAP4_UART3_DR1_SC_SHIFT				4
+#define OMAP4_UART3_DR1_SC_MASK					(0x3 << 4)
+#define OMAP4_UNIPRO_DR0_SC_SHIFT				2
+#define OMAP4_UNIPRO_DR0_SC_MASK				(0x3 << 2)
+#define OMAP4_UNIPRO_DR1_SC_SHIFT				0
+#define OMAP4_UNIPRO_DR1_SC_MASK				(0x3 << 0)
+
+/* CONTROL_SMART1IO_PADCONF_1 */
+#define OMAP4_ABE_DR0_LB_SHIFT					30
+#define OMAP4_ABE_DR0_LB_MASK					(0x3 << 30)
+#define OMAP4_CAM_DR0_LB_SHIFT					28
+#define OMAP4_CAM_DR0_LB_MASK					(0x3 << 28)
+#define OMAP4_FREF_DR2_LB_SHIFT					26
+#define OMAP4_FREF_DR2_LB_MASK					(0x3 << 26)
+#define OMAP4_FREF_DR3_LB_SHIFT					24
+#define OMAP4_FREF_DR3_LB_MASK					(0x3 << 24)
+#define OMAP4_GPIO_DR8_LB_SHIFT					22
+#define OMAP4_GPIO_DR8_LB_MASK					(0x3 << 22)
+#define OMAP4_GPIO_DR9_LB_SHIFT					20
+#define OMAP4_GPIO_DR9_LB_MASK					(0x3 << 20)
+#define OMAP4_GPMC_DR2_LB_SHIFT					18
+#define OMAP4_GPMC_DR2_LB_MASK					(0x3 << 18)
+#define OMAP4_GPMC_DR3_LB_SHIFT					16
+#define OMAP4_GPMC_DR3_LB_MASK					(0x3 << 16)
+#define OMAP4_GPMC_DR6_LB_SHIFT					14
+#define OMAP4_GPMC_DR6_LB_MASK					(0x3 << 14)
+#define OMAP4_HDMI_DR0_LB_SHIFT					12
+#define OMAP4_HDMI_DR0_LB_MASK					(0x3 << 12)
+#define OMAP4_MCSPI1_DR0_LB_SHIFT				10
+#define OMAP4_MCSPI1_DR0_LB_MASK				(0x3 << 10)
+#define OMAP4_UART1_DR0_LB_SHIFT				8
+#define OMAP4_UART1_DR0_LB_MASK					(0x3 << 8)
+#define OMAP4_UART3_DR0_LB_SHIFT				6
+#define OMAP4_UART3_DR0_LB_MASK					(0x3 << 6)
+#define OMAP4_UART3_DR1_LB_SHIFT				4
+#define OMAP4_UART3_DR1_LB_MASK					(0x3 << 4)
+#define OMAP4_UNIPRO_DR0_LB_SHIFT				2
+#define OMAP4_UNIPRO_DR0_LB_MASK				(0x3 << 2)
+#define OMAP4_UNIPRO_DR1_LB_SHIFT				0
+#define OMAP4_UNIPRO_DR1_LB_MASK				(0x3 << 0)
+
+/* CONTROL_SMART2IO_PADCONF_0 */
+#define OMAP4_C2C_DR0_LB_SHIFT					31
+#define OMAP4_C2C_DR0_LB_MASK					(1 << 31)
+#define OMAP4_DPM_DR1_LB_SHIFT					30
+#define OMAP4_DPM_DR1_LB_MASK					(1 << 30)
+#define OMAP4_DPM_DR2_LB_SHIFT					29
+#define OMAP4_DPM_DR2_LB_MASK					(1 << 29)
+#define OMAP4_DPM_DR3_LB_SHIFT					28
+#define OMAP4_DPM_DR3_LB_MASK					(1 << 28)
+#define OMAP4_GPIO_DR0_LB_SHIFT					27
+#define OMAP4_GPIO_DR0_LB_MASK					(1 << 27)
+#define OMAP4_GPIO_DR1_LB_SHIFT					26
+#define OMAP4_GPIO_DR1_LB_MASK					(1 << 26)
+#define OMAP4_GPIO_DR10_LB_SHIFT				25
+#define OMAP4_GPIO_DR10_LB_MASK					(1 << 25)
+#define OMAP4_GPIO_DR2_LB_SHIFT					24
+#define OMAP4_GPIO_DR2_LB_MASK					(1 << 24)
+#define OMAP4_GPMC_DR0_LB_SHIFT					23
+#define OMAP4_GPMC_DR0_LB_MASK					(1 << 23)
+#define OMAP4_GPMC_DR1_LB_SHIFT					22
+#define OMAP4_GPMC_DR1_LB_MASK					(1 << 22)
+#define OMAP4_GPMC_DR4_LB_SHIFT					21
+#define OMAP4_GPMC_DR4_LB_MASK					(1 << 21)
+#define OMAP4_GPMC_DR5_LB_SHIFT					20
+#define OMAP4_GPMC_DR5_LB_MASK					(1 << 20)
+#define OMAP4_GPMC_DR7_LB_SHIFT					19
+#define OMAP4_GPMC_DR7_LB_MASK					(1 << 19)
+#define OMAP4_HSI2_DR0_LB_SHIFT					18
+#define OMAP4_HSI2_DR0_LB_MASK					(1 << 18)
+#define OMAP4_HSI2_DR1_LB_SHIFT					17
+#define OMAP4_HSI2_DR1_LB_MASK					(1 << 17)
+#define OMAP4_HSI2_DR2_LB_SHIFT					16
+#define OMAP4_HSI2_DR2_LB_MASK					(1 << 16)
+#define OMAP4_KPD_DR0_LB_SHIFT					15
+#define OMAP4_KPD_DR0_LB_MASK					(1 << 15)
+#define OMAP4_KPD_DR1_LB_SHIFT					14
+#define OMAP4_KPD_DR1_LB_MASK					(1 << 14)
+#define OMAP4_PDM_DR0_LB_SHIFT					13
+#define OMAP4_PDM_DR0_LB_MASK					(1 << 13)
+#define OMAP4_SDMMC2_DR0_LB_SHIFT				12
+#define OMAP4_SDMMC2_DR0_LB_MASK				(1 << 12)
+#define OMAP4_SDMMC3_DR0_LB_SHIFT				11
+#define OMAP4_SDMMC3_DR0_LB_MASK				(1 << 11)