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@@ -222,3 +222,82 @@ titan_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
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csr = &port->port_specific.g.gtlbiv.csr;
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/* For TBIA, it doesn't matter what value we write. For TBI,
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+ it's the shifted tag bits. */
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+ value = (start & 0xffff0000) >> 12;
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+
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+ wmb();
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+ *csr = value;
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+ mb();
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+ *csr;
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+}
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+
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+static int
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+titan_query_agp(titan_pachip_port *port)
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+{
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+ union TPAchipPCTL pctl;
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+
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+ /* set up APCTL */
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+ pctl.pctl_q_whole = port->pctl.csr;
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+
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+ return pctl.pctl_r_bits.apctl_v_agp_present;
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+
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+}
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+
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+static void __init
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+titan_init_one_pachip_port(titan_pachip_port *port, int index)
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+{
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+ struct pci_controller *hose;
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+
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+ hose = alloc_pci_controller();
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+ if (index == 0)
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+ pci_isa_hose = hose;
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+ hose->io_space = alloc_resource();
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+ hose->mem_space = alloc_resource();
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+
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+ /*
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+ * This is for userland consumption. The 40-bit PIO bias that we
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+ * use in the kernel through KSEG doesn't work in the page table
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+ * based user mappings. (43-bit KSEG sign extends the physical
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+ * address from bit 40 to hit the I/O bit - mapped addresses don't).
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+ * So make sure we get the 43-bit PIO bias.
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+ */
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+ hose->sparse_mem_base = 0;
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+ hose->sparse_io_base = 0;
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+ hose->dense_mem_base
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+ = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL;
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+ hose->dense_io_base
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+ = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL;
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+
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+ hose->config_space_base = TITAN_CONF(index);
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+ hose->index = index;
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+
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+ hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS;
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+ hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1;
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+ hose->io_space->name = pci_io_names[index];
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+ hose->io_space->flags = IORESOURCE_IO;
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+
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+ hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS;
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+ hose->mem_space->end = hose->mem_space->start + 0xffffffff;
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+ hose->mem_space->name = pci_mem_names[index];
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+ hose->mem_space->flags = IORESOURCE_MEM;
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+
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+ if (request_resource(&ioport_resource, hose->io_space) < 0)
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+ printk(KERN_ERR "Failed to request IO on hose %d\n", index);
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+ if (request_resource(&iomem_resource, hose->mem_space) < 0)
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+ printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
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+
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+ /*
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+ * Save the existing PCI window translations. SRM will
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+ * need them when we go to reboot.
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+ */
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+ saved_config[index].wsba[0] = port->wsba[0].csr;
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+ saved_config[index].wsm[0] = port->wsm[0].csr;
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+ saved_config[index].tba[0] = port->tba[0].csr;
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+
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+ saved_config[index].wsba[1] = port->wsba[1].csr;
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+ saved_config[index].wsm[1] = port->wsm[1].csr;
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+ saved_config[index].tba[1] = port->tba[1].csr;
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+
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+ saved_config[index].wsba[2] = port->wsba[2].csr;
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+ saved_config[index].wsm[2] = port->wsm[2].csr;
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+ saved_config[index].tba[2] = port->tba[2].csr;
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