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@@ -1550,3 +1550,75 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
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pdev = &at91sam9g45_ssc1_device;
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configure_ssc1_pins(pins);
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break;
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+ default:
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+ return;
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+ }
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+
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+ platform_device_register(pdev);
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+}
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+
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+#else
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+void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
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+#endif
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+
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+
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+/* --------------------------------------------------------------------
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+ * UART
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+ * -------------------------------------------------------------------- */
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+
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+#if defined(CONFIG_SERIAL_ATMEL)
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+static struct resource dbgu_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9G45_BASE_DBGU,
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+ .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = NR_IRQS_LEGACY + AT91_ID_SYS,
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+ .end = NR_IRQS_LEGACY + AT91_ID_SYS,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct atmel_uart_data dbgu_data = {
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+ .use_dma_tx = 0,
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+ .use_dma_rx = 0,
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+};
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+
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+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
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+
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+static struct platform_device at91sam9g45_dbgu_device = {
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+ .name = "atmel_usart",
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+ .id = 0,
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+ .dev = {
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+ .dma_mask = &dbgu_dmamask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ .platform_data = &dbgu_data,
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+ },
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+ .resource = dbgu_resources,
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+ .num_resources = ARRAY_SIZE(dbgu_resources),
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+};
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+
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+static inline void configure_dbgu_pins(void)
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+{
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+ at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
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+ at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
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+}
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+
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+static struct resource uart0_resources[] = {
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+ [0] = {
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+ .start = AT91SAM9G45_BASE_US0,
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+ .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
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+ .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct atmel_uart_data uart0_data = {
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+ .use_dma_tx = 1,
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+ .use_dma_rx = 1,
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+};
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