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@@ -726,3 +726,195 @@ static struct clk_hw_omap lcd_gclk_hw = {
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DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops);
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DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
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+
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+static const char *gfx_ck_parents[] = {
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+ "dpll_core_m4_ck", "dpll_per_m2_ck",
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+};
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+
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+static const struct clksel gfx_clksel_sel[] = {
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+ { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
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+ { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
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+ { .parent = NULL },
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+};
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+
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+static struct clk gfx_fclk_clksel_ck;
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+
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+static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
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+ .hw = {
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+ .clk = &gfx_fclk_clksel_ck,
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+ },
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+ .clksel = gfx_clksel_sel,
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+ .clksel_reg = AM33XX_CLKSEL_GFX_FCLK,
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+ .clksel_mask = AM33XX_CLKSEL_GFX_FCLK_MASK,
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+};
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+
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+DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
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+
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+static const struct clk_div_table div_1_0_2_1_rates[] = {
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+ { .div = 1, .val = 0, },
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+ { .div = 2, .val = 1, },
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+ { .div = 0 },
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+};
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+
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+DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
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+ &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
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+ AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
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+ 0x0, div_1_0_2_1_rates, NULL);
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+
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+static const char *sysclkout_ck_parents[] = {
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+ "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
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+ "lcd_gclk",
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+};
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+
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+static const struct clksel sysclkout_pre_sel[] = {
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+ { .parent = &clk_32768_ck, .rates = div_1_0_rates },
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+ { .parent = &l3_gclk, .rates = div_1_1_rates },
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+ { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
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+ { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
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+ { .parent = &lcd_gclk, .rates = div_1_4_rates },
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+ { .parent = NULL },
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+};
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+
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+static struct clk sysclkout_pre_ck;
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+
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+static struct clk_hw_omap sysclkout_pre_ck_hw = {
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+ .hw = {
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+ .clk = &sysclkout_pre_ck,
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+ },
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+ .clksel = sysclkout_pre_sel,
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+ .clksel_reg = AM33XX_CM_CLKOUT_CTRL,
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+ .clksel_mask = AM33XX_CLKOUT2SOURCE_MASK,
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+};
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+
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+DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
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+
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+/* Divide by 8 clock rates with default clock is 1/1*/
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+static const struct clk_div_table div8_rates[] = {
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+ { .div = 1, .val = 0, },
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+ { .div = 2, .val = 1, },
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+ { .div = 3, .val = 2, },
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+ { .div = 4, .val = 3, },
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+ { .div = 5, .val = 4, },
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+ { .div = 6, .val = 5, },
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+ { .div = 7, .val = 6, },
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+ { .div = 8, .val = 7, },
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+ { .div = 0 },
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+};
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+
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+DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
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+ 0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
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+ AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
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+
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+DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
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+ AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
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+
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+static const char *wdt_ck_parents[] = {
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+ "clk_rc32k_ck", "clkdiv32k_ick",
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+};
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+
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+static const struct clksel wdt_clkmux_sel[] = {
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+ { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
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+ { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
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+ { .parent = NULL },
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+};
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+
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+static struct clk wdt1_fck;
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+
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+static struct clk_hw_omap wdt1_fck_hw = {
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+ .hw = {
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+ .clk = &wdt1_fck,
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+ },
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+ .clkdm_name = "l4_wkup_clkdm",
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+ .clksel = wdt_clkmux_sel,
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+ .clksel_reg = AM33XX_CLKSEL_WDT1_CLK,
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+ .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
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+};
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+
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+DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
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+
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+/*
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+ * clkdev
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+ */
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+static struct omap_clk am33xx_clks[] = {
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+ CLK(NULL, "clk_32768_ck", &clk_32768_ck, CK_AM33XX),
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+ CLK(NULL, "clk_rc32k_ck", &clk_rc32k_ck, CK_AM33XX),
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+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_AM33XX),
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+ CLK(NULL, "virt_24000000_ck", &virt_24000000_ck, CK_AM33XX),
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+ CLK(NULL, "virt_25000000_ck", &virt_25000000_ck, CK_AM33XX),
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+ CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_AM33XX),
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+ CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_AM33XX),
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+ CLK(NULL, "tclkin_ck", &tclkin_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_AM33XX),
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+ CLK("cpu0", NULL, &dpll_mpu_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_ddr_m2_div2_ck", &dpll_ddr_m2_div2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_disp_ck", &dpll_disp_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_disp_m2_ck", &dpll_disp_m2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", &dpll_per_m2_div4_wkupdm_ck, CK_AM33XX),
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+ CLK(NULL, "dpll_per_m2_div4_ck", &dpll_per_m2_div4_ck, CK_AM33XX),
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+ CLK(NULL, "adc_tsc_fck", &adc_tsc_fck, CK_AM33XX),
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+ CLK(NULL, "cefuse_fck", &cefuse_fck, CK_AM33XX),
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+ CLK(NULL, "clkdiv32k_ck", &clkdiv32k_ck, CK_AM33XX),
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+ CLK(NULL, "clkdiv32k_ick", &clkdiv32k_ick, CK_AM33XX),
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+ CLK(NULL, "dcan0_fck", &dcan0_fck, CK_AM33XX),
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+ CLK("481cc000.d_can", NULL, &dcan0_fck, CK_AM33XX),
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+ CLK(NULL, "dcan1_fck", &dcan1_fck, CK_AM33XX),
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+ CLK("481d0000.d_can", NULL, &dcan1_fck, CK_AM33XX),
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+ CLK(NULL, "debugss_ick", &debugss_ick, CK_AM33XX),
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+ CLK(NULL, "pruss_ocp_gclk", &pruss_ocp_gclk, CK_AM33XX),
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+ CLK(NULL, "mcasp0_fck", &mcasp0_fck, CK_AM33XX),
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+ CLK(NULL, "mcasp1_fck", &mcasp1_fck, CK_AM33XX),
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+ CLK(NULL, "mmu_fck", &mmu_fck, CK_AM33XX),
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+ CLK(NULL, "smartreflex0_fck", &smartreflex0_fck, CK_AM33XX),
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+ CLK(NULL, "smartreflex1_fck", &smartreflex1_fck, CK_AM33XX),
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+ CLK(NULL, "timer1_fck", &timer1_fck, CK_AM33XX),
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+ CLK(NULL, "timer2_fck", &timer2_fck, CK_AM33XX),
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+ CLK(NULL, "timer3_fck", &timer3_fck, CK_AM33XX),
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+ CLK(NULL, "timer4_fck", &timer4_fck, CK_AM33XX),
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+ CLK(NULL, "timer5_fck", &timer5_fck, CK_AM33XX),
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+ CLK(NULL, "timer6_fck", &timer6_fck, CK_AM33XX),
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+ CLK(NULL, "timer7_fck", &timer7_fck, CK_AM33XX),
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+ CLK(NULL, "usbotg_fck", &usbotg_fck, CK_AM33XX),
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+ CLK(NULL, "ieee5000_fck", &ieee5000_fck, CK_AM33XX),
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+ CLK(NULL, "wdt1_fck", &wdt1_fck, CK_AM33XX),
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+ CLK(NULL, "l4_rtc_gclk", &l4_rtc_gclk, CK_AM33XX),
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+ CLK(NULL, "l3_gclk", &l3_gclk, CK_AM33XX),
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+ CLK(NULL, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck, CK_AM33XX),
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+ CLK(NULL, "l4hs_gclk", &l4hs_gclk, CK_AM33XX),
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+ CLK(NULL, "l3s_gclk", &l3s_gclk, CK_AM33XX),
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+ CLK(NULL, "l4fw_gclk", &l4fw_gclk, CK_AM33XX),
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+ CLK(NULL, "l4ls_gclk", &l4ls_gclk, CK_AM33XX),
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+ CLK(NULL, "clk_24mhz", &clk_24mhz, CK_AM33XX),
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+ CLK(NULL, "sysclk_div_ck", &sysclk_div_ck, CK_AM33XX),
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+ CLK(NULL, "cpsw_125mhz_gclk", &cpsw_125mhz_gclk, CK_AM33XX),
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+ CLK(NULL, "cpsw_cpts_rft_clk", &cpsw_cpts_rft_clk, CK_AM33XX),
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+ CLK(NULL, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, CK_AM33XX),
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+ CLK(NULL, "gpio0_dbclk", &gpio0_dbclk, CK_AM33XX),
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+ CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_AM33XX),
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+ CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_AM33XX),
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+ CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_AM33XX),
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+ CLK(NULL, "lcd_gclk", &lcd_gclk, CK_AM33XX),
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+ CLK(NULL, "mmc_clk", &mmc_clk, CK_AM33XX),
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+ CLK(NULL, "gfx_fclk_clksel_ck", &gfx_fclk_clksel_ck, CK_AM33XX),
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+ CLK(NULL, "gfx_fck_div_ck", &gfx_fck_div_ck, CK_AM33XX),
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+ CLK(NULL, "sysclkout_pre_ck", &sysclkout_pre_ck, CK_AM33XX),
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+ CLK(NULL, "clkout2_div_ck", &clkout2_div_ck, CK_AM33XX),
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+ CLK(NULL, "timer_32k_ck", &clkdiv32k_ick, CK_AM33XX),
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+ CLK(NULL, "timer_sys_ck", &sys_clkin_ck, CK_AM33XX),
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+};
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+
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+
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+static const char *enable_init_clks[] = {
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+ "dpll_ddr_m2_ck",
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+ "dpll_mpu_m2_ck",
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+ "l3_gclk",
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+ "l4hs_gclk",
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袁明明