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@@ -1162,3 +1162,64 @@ static struct omap_ball __initdata omap4_core_cbs_ball[] = {
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_OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
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_OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
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_OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
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+ _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
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+ _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
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+ _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
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+ _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
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+ _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
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+ _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
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+ _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
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+ _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
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+ { .reg_offset = OMAP_MUX_TERMINATOR },
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+};
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+#else
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+#define omap4_core_cbs_ball NULL
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+#endif
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+
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+/*
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+ * Superset of all mux modes for omap4
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+ */
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+static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
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+ _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
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+ NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
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+ NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
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+ NULL, NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
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+ NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
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+ NULL, NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
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+ NULL, NULL),
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+ _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
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+ NULL, NULL),
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+ _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
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+ "c2c_wakereqin", NULL, NULL, NULL),
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+ _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
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+ "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
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+ _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
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