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@@ -290,3 +290,132 @@
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/* PM_EVGENCTRL_MPU */
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/* PM_EVGENCTRL_MPU */
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#define OMAP3430_OFFLOADMODE_SHIFT 3
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#define OMAP3430_OFFLOADMODE_SHIFT 3
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+#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
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+#define OMAP3430_ONLOADMODE_SHIFT 1
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+#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
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+#define OMAP3430_ENABLE_MASK (1 << 0)
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+
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+/* PM_EVGENONTIM_MPU */
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+#define OMAP3430_ONTIMEVAL_SHIFT 0
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+#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
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+
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+/* PM_EVGENOFFTIM_MPU */
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+#define OMAP3430_OFFTIMEVAL_SHIFT 0
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+#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
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+
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+/* PM_PWSTCTRL_MPU specific bits */
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+#define OMAP3430_L2CACHEONSTATE_SHIFT 16
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+#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
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+#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
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+#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
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+
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+/* PM_PWSTST_MPU specific bits */
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+#define OMAP3430_L2CACHESTATEST_SHIFT 6
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+#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
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+#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
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+
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+/* PM_PREPWSTST_MPU specific bits */
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+#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
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+#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
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+#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
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+
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+/* RM_RSTCTRL_CORE */
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+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
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+#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
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+
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+/* RM_RSTST_CORE specific bits */
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+#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
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+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
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+#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
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+
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+/* PM_WKEN1_CORE specific bits */
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+
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+/* PM_MPUGRPSEL1_CORE specific bits */
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+#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
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+
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+/* PM_IVA2GRPSEL1_CORE specific bits */
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+
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+/* PM_WKST1_CORE specific bits */
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+
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+/* PM_PWSTCTRL_CORE specific bits */
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+#define OMAP3430_MEM2ONSTATE_SHIFT 18
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+#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
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+#define OMAP3430_MEM1ONSTATE_SHIFT 16
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+#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
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+#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
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+#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
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+
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+/* PM_PWSTST_CORE specific bits */
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+#define OMAP3430_MEM2STATEST_SHIFT 6
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+#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
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+#define OMAP3430_MEM1STATEST_SHIFT 4
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+#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
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+
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+/* PM_PREPWSTST_CORE specific bits */
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+#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
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+#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
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+#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
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+#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
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+
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+/* RM_RSTST_GFX specific bits */
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+
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+/* PM_WKDEP_GFX specific bits */
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+#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
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+
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+/* PM_PWSTCTRL_GFX specific bits */
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+
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+/* PM_PWSTST_GFX specific bits */
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+
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+/* PM_PREPWSTST_GFX specific bits */
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+
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+/* PM_WKEN_WKUP specific bits */
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+#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
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+#define OMAP3430_EN_IO_MASK (1 << 8)
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+#define OMAP3430_EN_GPIO1_MASK (1 << 3)
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+
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+/* PM_MPUGRPSEL_WKUP specific bits */
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+
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+/* PM_IVA2GRPSEL_WKUP specific bits */
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+
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+/* PM_WKST_WKUP specific bits */
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+#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
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+#define OMAP3430_ST_IO_MASK (1 << 8)
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+
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+/* PRM_CLKSEL */
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+#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
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+#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
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+#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
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+
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+/* PRM_CLKOUT_CTRL */
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+#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
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+#define OMAP3430_CLKOUT_EN_SHIFT 7
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+
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+/* RM_RSTST_DSS specific bits */
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+
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+/* PM_WKEN_DSS */
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+#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
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+
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+/* PM_WKDEP_DSS specific bits */
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+#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
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+
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+/* PM_PWSTCTRL_DSS specific bits */
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+
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+/* PM_PWSTST_DSS specific bits */
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+
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+/* PM_PREPWSTST_DSS specific bits */
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+
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+/* RM_RSTST_CAM specific bits */
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+
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+/* PM_WKDEP_CAM specific bits */
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+#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
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+
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+/* PM_PWSTCTRL_CAM specific bits */
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+
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+/* PM_PWSTST_CAM specific bits */
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+
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+/* PM_PREPWSTST_CAM specific bits */
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+
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+/* PM_PWSTCTRL_USBHOST specific bits */
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+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
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+
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+/* RM_RSTST_PER specific bits */
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