|  | @@ -290,3 +290,132 @@
 | 
	
		
			
				|  |  |  
 | 
	
		
			
				|  |  |  /* PM_EVGENCTRL_MPU */
 | 
	
		
			
				|  |  |  #define OMAP3430_OFFLOADMODE_SHIFT			3
 | 
	
		
			
				|  |  | +#define OMAP3430_OFFLOADMODE_MASK			(0x3 << 3)
 | 
	
		
			
				|  |  | +#define OMAP3430_ONLOADMODE_SHIFT			1
 | 
	
		
			
				|  |  | +#define OMAP3430_ONLOADMODE_MASK			(0x3 << 1)
 | 
	
		
			
				|  |  | +#define OMAP3430_ENABLE_MASK				(1 << 0)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_EVGENONTIM_MPU */
 | 
	
		
			
				|  |  | +#define OMAP3430_ONTIMEVAL_SHIFT			0
 | 
	
		
			
				|  |  | +#define OMAP3430_ONTIMEVAL_MASK				(0xffffffff << 0)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_EVGENOFFTIM_MPU */
 | 
	
		
			
				|  |  | +#define OMAP3430_OFFTIMEVAL_SHIFT			0
 | 
	
		
			
				|  |  | +#define OMAP3430_OFFTIMEVAL_MASK			(0xffffffff << 0)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_MPU specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_L2CACHEONSTATE_SHIFT			16
 | 
	
		
			
				|  |  | +#define OMAP3430_L2CACHEONSTATE_MASK			(0x3 << 16)
 | 
	
		
			
				|  |  | +#define OMAP3430_L2CACHERETSTATE_MASK			(1 << 8)
 | 
	
		
			
				|  |  | +#define OMAP3430_LOGICL1CACHERETSTATE_MASK		(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTST_MPU specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_L2CACHESTATEST_SHIFT			6
 | 
	
		
			
				|  |  | +#define OMAP3430_L2CACHESTATEST_MASK			(0x3 << 6)
 | 
	
		
			
				|  |  | +#define OMAP3430_LOGICL1CACHESTATEST_MASK		(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PREPWSTST_MPU specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT		6
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTL2CACHESTATEENTERED_MASK		(0x3 << 6)
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK	(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTCTRL_CORE */
 | 
	
		
			
				|  |  | +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK		(1 << 1)
 | 
	
		
			
				|  |  | +#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK		(1 << 0)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTST_CORE specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK		(1 << 10)
 | 
	
		
			
				|  |  | +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK	(1 << 9)
 | 
	
		
			
				|  |  | +#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK	(1 << 8)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKEN1_CORE specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_MPUGRPSEL1_CORE specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_GRPSEL_FSHOSTUSB_MASK			(1 << 5)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_IVA2GRPSEL1_CORE specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKST1_CORE specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_CORE specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM2ONSTATE_SHIFT			18
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM2ONSTATE_MASK			(0x3 << 18)
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM1ONSTATE_SHIFT			16
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM1ONSTATE_MASK			(0x3 << 16)
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM2RETSTATE_MASK			(1 << 9)
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM1RETSTATE_MASK			(1 << 8)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTST_CORE specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM2STATEST_SHIFT			6
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM2STATEST_MASK			(0x3 << 6)
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM1STATEST_SHIFT			4
 | 
	
		
			
				|  |  | +#define OMAP3430_MEM1STATEST_MASK			(0x3 << 4)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PREPWSTST_CORE specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTMEM2STATEENTERED_SHIFT		6
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTMEM2STATEENTERED_MASK		(0x3 << 6)
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTMEM1STATEENTERED_SHIFT		4
 | 
	
		
			
				|  |  | +#define OMAP3430_LASTMEM1STATEENTERED_MASK		(0x3 << 4)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTST_GFX specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKDEP_GFX specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK		(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_GFX specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTST_GFX specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PREPWSTST_GFX specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKEN_WKUP specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_EN_IO_CHAIN_MASK			(1 << 16)
 | 
	
		
			
				|  |  | +#define OMAP3430_EN_IO_MASK				(1 << 8)
 | 
	
		
			
				|  |  | +#define OMAP3430_EN_GPIO1_MASK				(1 << 3)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_MPUGRPSEL_WKUP specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_IVA2GRPSEL_WKUP specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKST_WKUP specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_ST_IO_CHAIN_MASK			(1 << 16)
 | 
	
		
			
				|  |  | +#define OMAP3430_ST_IO_MASK				(1 << 8)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PRM_CLKSEL */
 | 
	
		
			
				|  |  | +#define OMAP3430_SYS_CLKIN_SEL_SHIFT			0
 | 
	
		
			
				|  |  | +#define OMAP3430_SYS_CLKIN_SEL_MASK			(0x7 << 0)
 | 
	
		
			
				|  |  | +#define OMAP3430_SYS_CLKIN_SEL_WIDTH			3
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PRM_CLKOUT_CTRL */
 | 
	
		
			
				|  |  | +#define OMAP3430_CLKOUT_EN_MASK				(1 << 7)
 | 
	
		
			
				|  |  | +#define OMAP3430_CLKOUT_EN_SHIFT			7
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTST_DSS specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKEN_DSS */
 | 
	
		
			
				|  |  | +#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK		(1 << 0)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKDEP_DSS specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK		(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_DSS specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTST_DSS specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PREPWSTST_DSS specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTST_CAM specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_WKDEP_CAM specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK		(1 << 2)
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_CAM specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTST_CAM specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PREPWSTST_CAM specific bits */
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* PM_PWSTCTRL_USBHOST specific bits */
 | 
	
		
			
				|  |  | +#define OMAP3430ES2_SAVEANDRESTORE_SHIFT		4
 | 
	
		
			
				|  |  | +
 | 
	
		
			
				|  |  | +/* RM_RSTST_PER specific bits */
 |