efHotAgingTrendMining dataMonitoring.h 朱俊杰 commit at 2021-03-25

efHotAgingTrendMining/externalListeningThread/dataMonitoring.h

@@ -178,3 +178,69 @@
 
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
 #define OMAP24XX_ST_GPIOS_SHIFT				2
+#define OMAP24XX_ST_GPIOS_MASK				(1 << 2)
+#define OMAP24XX_ST_32KSYNC_SHIFT			1
+#define OMAP24XX_ST_32KSYNC_MASK			(1 << 1)
+#define OMAP24XX_ST_GPT1_SHIFT				0
+#define OMAP24XX_ST_GPT1_MASK				(1 << 0)
+
+/* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
+#define OMAP2430_ST_MDM_SHIFT				0
+#define OMAP2430_ST_MDM_MASK				(1 << 0)
+
+
+/* 3430 register bits shared between CM & PRM registers */
+
+/* CM_REVISION, PRM_REVISION shared bits */
+#define OMAP3430_REV_SHIFT				0
+#define OMAP3430_REV_MASK				(0xff << 0)
+
+/* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
+#define OMAP3430_AUTOIDLE_MASK				(1 << 0)
+
+/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC3_MASK				(1 << 30)
+#define OMAP3430_EN_MMC3_SHIFT				30
+#define OMAP3430_EN_MMC2_MASK				(1 << 25)
+#define OMAP3430_EN_MMC2_SHIFT				25
+#define OMAP3430_EN_MMC1_MASK				(1 << 24)
+#define OMAP3430_EN_MMC1_SHIFT				24
+#define AM35XX_EN_UART4_MASK				(1 << 23)
+#define AM35XX_EN_UART4_SHIFT				23
+#define OMAP3430_EN_MCSPI4_MASK				(1 << 21)
+#define OMAP3430_EN_MCSPI4_SHIFT			21
+#define OMAP3430_EN_MCSPI3_MASK				(1 << 20)
+#define OMAP3430_EN_MCSPI3_SHIFT			20
+#define OMAP3430_EN_MCSPI2_MASK				(1 << 19)
+#define OMAP3430_EN_MCSPI2_SHIFT			19
+#define OMAP3430_EN_MCSPI1_MASK				(1 << 18)
+#define OMAP3430_EN_MCSPI1_SHIFT			18
+#define OMAP3430_EN_I2C3_MASK				(1 << 17)
+#define OMAP3430_EN_I2C3_SHIFT				17
+#define OMAP3430_EN_I2C2_MASK				(1 << 16)
+#define OMAP3430_EN_I2C2_SHIFT				16
+#define OMAP3430_EN_I2C1_MASK				(1 << 15)
+#define OMAP3430_EN_I2C1_SHIFT				15
+#define OMAP3430_EN_UART2_MASK				(1 << 14)
+#define OMAP3430_EN_UART2_SHIFT				14
+#define OMAP3430_EN_UART1_MASK				(1 << 13)
+#define OMAP3430_EN_UART1_SHIFT				13
+#define OMAP3430_EN_GPT11_MASK				(1 << 12)
+#define OMAP3430_EN_GPT11_SHIFT				12
+#define OMAP3430_EN_GPT10_MASK				(1 << 11)
+#define OMAP3430_EN_GPT10_SHIFT				11
+#define OMAP3430_EN_MCBSP5_MASK				(1 << 10)
+#define OMAP3430_EN_MCBSP5_SHIFT			10
+#define OMAP3430_EN_MCBSP1_MASK				(1 << 9)
+#define OMAP3430_EN_MCBSP1_SHIFT			9
+#define OMAP3430_EN_FSHOSTUSB_MASK			(1 << 5)
+#define OMAP3430_EN_FSHOSTUSB_SHIFT			5
+#define OMAP3430_EN_D2D_MASK				(1 << 3)
+#define OMAP3430_EN_D2D_SHIFT				3
+
+/* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_HSOTGUSB_MASK			(1 << 4)
+#define OMAP3430_EN_HSOTGUSB_SHIFT			4
+
+/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC3_SHIFT				30