|
@@ -1366,3 +1366,150 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
|
|
|
.mpu_irqs = omap44xx_gpmc_irqs,
|
|
|
.sdma_reqs = omap44xx_gpmc_sdma_reqs,
|
|
|
.prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_HWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'gpu' class
|
|
|
+ * 2d/3d graphics accelerator
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
|
|
|
+ .rev_offs = 0x1fc00,
|
|
|
+ .sysc_offs = 0x1fc10,
|
|
|
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
|
|
|
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
|
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type2,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
|
|
|
+ .name = "gpu",
|
|
|
+ .sysc = &omap44xx_gpu_sysc,
|
|
|
+};
|
|
|
+
|
|
|
+/* gpu */
|
|
|
+static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
|
|
|
+ { .irq = 21 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .irq = -1 }
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_gpu_hwmod = {
|
|
|
+ .name = "gpu",
|
|
|
+ .class = &omap44xx_gpu_hwmod_class,
|
|
|
+ .clkdm_name = "l3_gfx_clkdm",
|
|
|
+ .mpu_irqs = omap44xx_gpu_irqs,
|
|
|
+ .main_clk = "gpu_fck",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'hdq1w' class
|
|
|
+ * hdq / 1-wire serial interface controller
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
|
|
|
+ .rev_offs = 0x0000,
|
|
|
+ .sysc_offs = 0x0014,
|
|
|
+ .syss_offs = 0x0018,
|
|
|
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
|
|
|
+ SYSS_HAS_RESET_STATUS),
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
|
|
|
+ .name = "hdq1w",
|
|
|
+ .sysc = &omap44xx_hdq1w_sysc,
|
|
|
+};
|
|
|
+
|
|
|
+/* hdq1w */
|
|
|
+static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
|
|
|
+ { .irq = 58 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .irq = -1 }
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_hdq1w_hwmod = {
|
|
|
+ .name = "hdq1w",
|
|
|
+ .class = &omap44xx_hdq1w_hwmod_class,
|
|
|
+ .clkdm_name = "l4_per_clkdm",
|
|
|
+ .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
|
|
|
+ .mpu_irqs = omap44xx_hdq1w_irqs,
|
|
|
+ .main_clk = "hdq1w_fck",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'hsi' class
|
|
|
+ * mipi high-speed synchronous serial interface (multichannel and full-duplex
|
|
|
+ * serial if)
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
|
|
|
+ .rev_offs = 0x0000,
|
|
|
+ .sysc_offs = 0x0010,
|
|
|
+ .syss_offs = 0x0014,
|
|
|
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
|
|
|
+ SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
|
|
|
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
|
|
|
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
|
|
|
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
|
|
|
+ .name = "hsi",
|
|
|
+ .sysc = &omap44xx_hsi_sysc,
|
|
|
+};
|
|
|
+
|
|
|
+/* hsi */
|
|
|
+static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
|
|
|
+ { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
|
|
|
+ { .irq = -1 }
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod omap44xx_hsi_hwmod = {
|
|
|
+ .name = "hsi",
|
|
|
+ .class = &omap44xx_hsi_hwmod_class,
|
|
|
+ .clkdm_name = "l3_init_clkdm",
|
|
|
+ .mpu_irqs = omap44xx_hsi_irqs,
|
|
|
+ .main_clk = "hsi_fck",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_HWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+/*
|
|
|
+ * 'i2c' class
|
|
|
+ * multimaster high-speed i2c controller
|
|
|
+ */
|
|
|
+
|
|
|
+static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
|
|
|
+ .sysc_offs = 0x0010,
|
|
|
+ .syss_offs = 0x0090,
|
|
|
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
|
|
|
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
|