|  | @@ -1366,3 +1366,150 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
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				|  |  |  	.mpu_irqs	= omap44xx_gpmc_irqs,
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				|  |  |  	.sdma_reqs	= omap44xx_gpmc_sdma_reqs,
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				|  |  |  	.prcm = {
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				|  |  | +		.omap4 = {
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				|  |  | +			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
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				|  |  | +			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
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				|  |  | +			.modulemode   = MODULEMODE_HWCTRL,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +};
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * 'gpu' class
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				|  |  | + * 2d/3d graphics accelerator
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				|  |  | + */
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
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				|  |  | +	.rev_offs	= 0x1fc00,
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				|  |  | +	.sysc_offs	= 0x1fc10,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
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				|  |  | +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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				|  |  | +			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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				|  |  | +			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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				|  |  | +	.sysc_fields	= &omap_hwmod_sysc_type2,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
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				|  |  | +	.name	= "gpu",
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				|  |  | +	.sysc	= &omap44xx_gpu_sysc,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* gpu */
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				|  |  | +static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
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				|  |  | +	{ .irq = 21 + OMAP44XX_IRQ_GIC_START },
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				|  |  | +	{ .irq = -1 }
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap44xx_gpu_hwmod = {
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				|  |  | +	.name		= "gpu",
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				|  |  | +	.class		= &omap44xx_gpu_hwmod_class,
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				|  |  | +	.clkdm_name	= "l3_gfx_clkdm",
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				|  |  | +	.mpu_irqs	= omap44xx_gpu_irqs,
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				|  |  | +	.main_clk	= "gpu_fck",
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				|  |  | +	.prcm = {
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				|  |  | +		.omap4 = {
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				|  |  | +			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
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				|  |  | +			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
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				|  |  | +			.modulemode   = MODULEMODE_SWCTRL,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +};
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * 'hdq1w' class
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				|  |  | + * hdq / 1-wire serial interface controller
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				|  |  | + */
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
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				|  |  | +	.rev_offs	= 0x0000,
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				|  |  | +	.sysc_offs	= 0x0014,
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				|  |  | +	.syss_offs	= 0x0018,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
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				|  |  | +			   SYSS_HAS_RESET_STATUS),
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				|  |  | +	.sysc_fields	= &omap_hwmod_sysc_type1,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
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				|  |  | +	.name	= "hdq1w",
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				|  |  | +	.sysc	= &omap44xx_hdq1w_sysc,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* hdq1w */
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				|  |  | +static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
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				|  |  | +	{ .irq = 58 + OMAP44XX_IRQ_GIC_START },
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				|  |  | +	{ .irq = -1 }
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap44xx_hdq1w_hwmod = {
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				|  |  | +	.name		= "hdq1w",
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				|  |  | +	.class		= &omap44xx_hdq1w_hwmod_class,
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				|  |  | +	.clkdm_name	= "l4_per_clkdm",
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				|  |  | +	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
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				|  |  | +	.mpu_irqs	= omap44xx_hdq1w_irqs,
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				|  |  | +	.main_clk	= "hdq1w_fck",
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				|  |  | +	.prcm = {
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				|  |  | +		.omap4 = {
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				|  |  | +			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
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				|  |  | +			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
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				|  |  | +			.modulemode   = MODULEMODE_SWCTRL,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +};
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * 'hsi' class
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				|  |  | + * mipi high-speed synchronous serial interface (multichannel and full-duplex
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				|  |  | + * serial if)
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				|  |  | + */
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
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				|  |  | +	.rev_offs	= 0x0000,
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				|  |  | +	.sysc_offs	= 0x0010,
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				|  |  | +	.syss_offs	= 0x0014,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
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				|  |  | +			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
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				|  |  | +			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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				|  |  | +	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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				|  |  | +			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
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				|  |  | +			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
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				|  |  | +	.sysc_fields	= &omap_hwmod_sysc_type1,
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
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				|  |  | +	.name	= "hsi",
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				|  |  | +	.sysc	= &omap44xx_hsi_sysc,
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				|  |  | +};
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				|  |  | +
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				|  |  | +/* hsi */
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				|  |  | +static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
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				|  |  | +	{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
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				|  |  | +	{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
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				|  |  | +	{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
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				|  |  | +	{ .irq = -1 }
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				|  |  | +};
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				|  |  | +
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				|  |  | +static struct omap_hwmod omap44xx_hsi_hwmod = {
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				|  |  | +	.name		= "hsi",
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				|  |  | +	.class		= &omap44xx_hsi_hwmod_class,
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				|  |  | +	.clkdm_name	= "l3_init_clkdm",
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				|  |  | +	.mpu_irqs	= omap44xx_hsi_irqs,
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				|  |  | +	.main_clk	= "hsi_fck",
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				|  |  | +	.prcm = {
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				|  |  | +		.omap4 = {
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				|  |  | +			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
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				|  |  | +			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
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				|  |  | +			.modulemode   = MODULEMODE_HWCTRL,
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				|  |  | +		},
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				|  |  | +	},
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				|  |  | +};
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				|  |  | +
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				|  |  | +/*
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				|  |  | + * 'i2c' class
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				|  |  | + * multimaster high-speed i2c controller
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				|  |  | + */
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				|  |  | +
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				|  |  | +static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
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				|  |  | +	.sysc_offs	= 0x0010,
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				|  |  | +	.syss_offs	= 0x0090,
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				|  |  | +	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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				|  |  | +			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
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