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@@ -558,3 +558,131 @@ static struct omap_board_mux omap35x_board_mux[] __initdata = {
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OMAP_PIN_OFF_WAKEUPENABLE),
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OMAP_PIN_OFF_WAKEUPENABLE),
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OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
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OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
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OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
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OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
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+ OMAP_PIN_OFF_WAKEUPENABLE),
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+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
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+ OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
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+ OMAP_PIN_OFF_NONE),
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+#ifdef CONFIG_WL12XX_PLATFORM_DATA
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+ /* WLAN IRQ - GPIO 149 */
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+ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
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+
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+ /* WLAN POWER ENABLE - GPIO 150 */
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+ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
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+
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+ /* MMC2 SDIO pin muxes for WL12xx */
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+ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+#endif
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+ { .reg_offset = OMAP_MUX_TERMINATOR },
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+};
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+
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+static struct omap_board_mux omap36x_board_mux[] __initdata = {
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+ OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
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+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
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+ OMAP_PIN_OFF_WAKEUPENABLE),
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+ OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
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+ OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
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+ OMAP_PIN_OFF_WAKEUPENABLE),
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+ /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
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+ OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+ OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
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+#ifdef CONFIG_WL12XX_PLATFORM_DATA
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+ /* WLAN IRQ - GPIO 149 */
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+ OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
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+
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+ /* WLAN POWER ENABLE - GPIO 150 */
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+ OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
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+
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+ /* MMC2 SDIO pin muxes for WL12xx */
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+ OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+ OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
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+#endif
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+
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+ { .reg_offset = OMAP_MUX_TERMINATOR },
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+};
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+#else
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+#define omap35x_board_mux NULL
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+#define omap36x_board_mux NULL
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+#endif
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+
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+static struct omap_musb_board_data musb_board_data = {
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+ .interface_type = MUSB_INTERFACE_ULPI,
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+ .mode = MUSB_OTG,
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+ .power = 100,
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+};
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+
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+static struct gpio omap3_evm_ehci_gpios[] __initdata = {
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+ { OMAP3_EVM_EHCI_VBUS, GPIOF_OUT_INIT_HIGH, "enable EHCI VBUS" },
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+ { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW, "select EHCI port" },
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+};
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+
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+static void __init omap3_evm_wl12xx_init(void)
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+{
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+#ifdef CONFIG_WL12XX_PLATFORM_DATA
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+ int ret;
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+
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+ /* WL12xx WLAN Init */
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+ omap3evm_wlan_data.irq = gpio_to_irq(OMAP3EVM_WLAN_IRQ_GPIO);
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+ ret = wl12xx_set_platform_data(&omap3evm_wlan_data);
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+ if (ret)
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+ pr_err("error setting wl12xx data: %d\n", ret);
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+ ret = platform_device_register(&omap3evm_wlan_regulator);
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+ if (ret)
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+ pr_err("error registering wl12xx device: %d\n", ret);
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+#endif
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+}
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+
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+static struct regulator_consumer_supply dummy_supplies[] = {
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+ REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
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+ REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
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+};
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+
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+static struct mtd_partition omap3evm_nand_partitions[] = {
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+ /* All the partition sizes are listed in terms of NAND block size */
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+ {
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+ .name = "X-Loader",
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+ .offset = 0,
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+ .size = 4*(SZ_128K),
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+ .mask_flags = MTD_WRITEABLE
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+ },
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+ {
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+ .name = "U-Boot",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 14*(SZ_128K),
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+ .mask_flags = MTD_WRITEABLE
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+ },
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+ {
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+ .name = "U-Boot Env",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 2*(SZ_128K)
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+ },
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+ {
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+ .name = "Kernel",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 40*(SZ_128K)
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+ },
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+ {
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+ .name = "File system",
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+ .size = MTDPART_SIZ_FULL,
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+ .offset = MTDPART_OFS_APPEND,
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+ },
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+};
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