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@@ -777,3 +777,90 @@ static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
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};
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struct omap_hwmod omap2xxx_counter_32k_hwmod = {
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+ .name = "counter_32k",
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+ .main_clk = "func_32k_ck",
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+ .prcm = {
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+ .omap2 = {
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+ .module_offs = WKUP_MOD,
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
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+ },
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+ },
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+ .class = &omap2xxx_counter_hwmod_class,
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+};
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+
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+/* gpmc */
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+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
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+ { .irq = 20 },
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+ { .irq = -1 }
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+};
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+
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+struct omap_hwmod omap2xxx_gpmc_hwmod = {
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+ .name = "gpmc",
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+ .class = &omap2xxx_gpmc_hwmod_class,
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+ .mpu_irqs = omap2xxx_gpmc_irqs,
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+ .main_clk = "gpmc_fck",
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+ /*
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+ * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
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+ * block. It is not being added due to any known bugs with
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+ * resetting the GPMC IP block, but rather because any timings
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+ * set by the bootloader are not being correctly programmed by
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+ * the kernel from the board file or DT data.
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+ * HWMOD_INIT_NO_RESET should be removed ASAP.
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+ */
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+ .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
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+ HWMOD_NO_IDLEST),
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 3,
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+ .module_bit = OMAP24XX_EN_GPMC_MASK,
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+ .module_offs = CORE_MOD,
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+ },
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+ },
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+};
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+
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+/* RNG */
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+
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+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
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+ .rev_offs = 0x3c,
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+ .sysc_offs = 0x40,
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+ .syss_offs = 0x44,
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+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
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+ SYSS_HAS_RESET_STATUS),
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+ .sysc_fields = &omap_hwmod_sysc_type1,
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+};
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+
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+static struct omap_hwmod_class omap2_rng_hwmod_class = {
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+ .name = "rng",
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+ .sysc = &omap2_rng_sysc,
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+};
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+
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+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
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+ { .irq = 52 },
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+ { .irq = -1 }
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+};
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+
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+struct omap_hwmod omap2xxx_rng_hwmod = {
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+ .name = "rng",
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+ .mpu_irqs = omap2_rng_mpu_irqs,
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+ .main_clk = "l4_ck",
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+ .prcm = {
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+ .omap2 = {
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+ .module_offs = CORE_MOD,
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+ .prcm_reg_id = 4,
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+ .module_bit = OMAP24XX_EN_RNG_SHIFT,
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+ .idlest_reg_id = 4,
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+ .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
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+ },
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+ },
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+ /*
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+ * XXX The first read from the SYSSTATUS register of the RNG
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+ * after the SYSCONFIG SOFTRESET bit is set triggers an
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+ * imprecise external abort. It's unclear why this happens.
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+ * Until this is analyzed, skip the IP block reset.
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+ */
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+ .flags = HWMOD_INIT_NO_RESET,
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+ .class = &omap2_rng_hwmod_class,
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+};
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