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@@ -244,3 +244,79 @@ static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
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/* pwm timers dev attribute */
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static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
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+ .timer_capability = OMAP_TIMER_HAS_PWM,
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+};
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+
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+/* timers with DSP interrupt dev attribute */
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+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
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+ .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
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+};
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+
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+/* timer1 */
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+
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+struct omap_hwmod omap2xxx_timer1_hwmod = {
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+ .name = "timer1",
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+ .mpu_irqs = omap2_timer1_mpu_irqs,
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+ .main_clk = "gpt1_fck",
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP24XX_EN_GPT1_SHIFT,
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+ .module_offs = WKUP_MOD,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
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+ },
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+ },
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+ .dev_attr = &capability_alwon_dev_attr,
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+ .class = &omap2xxx_timer_hwmod_class,
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+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
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+};
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+
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+/* timer2 */
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+
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+struct omap_hwmod omap2xxx_timer2_hwmod = {
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+ .name = "timer2",
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+ .mpu_irqs = omap2_timer2_mpu_irqs,
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+ .main_clk = "gpt2_fck",
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP24XX_EN_GPT2_SHIFT,
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+ .module_offs = CORE_MOD,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
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+ },
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+ },
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+ .class = &omap2xxx_timer_hwmod_class,
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+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
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+};
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+
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+/* timer3 */
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+
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+struct omap_hwmod omap2xxx_timer3_hwmod = {
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+ .name = "timer3",
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+ .mpu_irqs = omap2_timer3_mpu_irqs,
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+ .main_clk = "gpt3_fck",
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP24XX_EN_GPT3_SHIFT,
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+ .module_offs = CORE_MOD,
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+ .idlest_reg_id = 1,
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+ .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
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+ },
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+ },
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+ .class = &omap2xxx_timer_hwmod_class,
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+ .flags = HWMOD_SET_DEFAULT_CLOCKACT,
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+};
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+
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+/* timer4 */
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+
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+struct omap_hwmod omap2xxx_timer4_hwmod = {
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+ .name = "timer4",
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+ .mpu_irqs = omap2_timer4_mpu_irqs,
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+ .main_clk = "gpt4_fck",
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+ .prcm = {
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+ .omap2 = {
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+ .prcm_reg_id = 1,
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+ .module_bit = OMAP24XX_EN_GPT4_SHIFT,
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