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+/*
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+ * linux/arch/arm/mach-sa1100/cpu-sa1110.c
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+ *
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+ * Copyright (C) 2001 Russell King
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Note: there are two erratas that apply to the SA1110 here:
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+ * 7 - SDRAM auto-power-up failure (rev A0)
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+ * 13 - Corruption of internal register reads/writes following
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+ * SDRAM reads (rev A0, B0, B1)
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+ *
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+ * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
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+ *
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+ * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
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+ */
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+#include <linux/cpufreq.h>
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+#include <linux/delay.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/moduleparam.h>
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+#include <linux/types.h>
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+
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+#include <asm/cputype.h>
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+#include <asm/mach-types.h>
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+
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+#include <mach/hardware.h>
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+
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+#include "generic.h"
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+
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+#undef DEBUG
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+
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+struct sdram_params {
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+ const char name[20];
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+ u_char rows; /* bits */
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+ u_char cas_latency; /* cycles */
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+ u_char tck; /* clock cycle time (ns) */
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+ u_char trcd; /* activate to r/w (ns) */
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+ u_char trp; /* precharge to activate (ns) */
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+ u_char twr; /* write recovery time (ns) */
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+ u_short refresh; /* refresh time for array (us) */
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+};
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+
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+struct sdram_info {
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+ u_int mdcnfg;
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+ u_int mdrefr;
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+ u_int mdcas[3];
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+};
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+
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+static struct sdram_params sdram_tbl[] __initdata = {
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+ { /* Toshiba TC59SM716 CL2 */
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+ .name = "TC59SM716-CL2",
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+ .rows = 12,
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+ .tck = 10,
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+ .trcd = 20,
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+ .trp = 20,
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+ .twr = 10,
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+ .refresh = 64000,
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+ .cas_latency = 2,
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+ }, { /* Toshiba TC59SM716 CL3 */
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+ .name = "TC59SM716-CL3",
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+ .rows = 12,
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+ .tck = 8,
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+ .trcd = 20,
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+ .trp = 20,
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+ .twr = 8,
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ }, { /* Samsung K4S641632D TC75 */
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+ .name = "K4S641632D",
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+ .rows = 14,
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+ .tck = 9,
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+ .trcd = 27,
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+ .trp = 20,
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+ .twr = 9,
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ }, { /* Samsung K4S281632B-1H */
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+ .name = "K4S281632B-1H",
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+ .rows = 12,
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+ .tck = 10,
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+ .trp = 20,
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+ .twr = 10,
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ }, { /* Samsung KM416S4030CT */
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+ .name = "KM416S4030CT",
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+ .rows = 13,
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+ .tck = 8,
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+ .trcd = 24, /* 3 CLKs */
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+ .trp = 24, /* 3 CLKs */
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+ .twr = 16, /* Trdl: 2 CLKs */
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ }, { /* Winbond W982516AH75L CL3 */
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+ .name = "W982516AH75L",
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+ .rows = 16,
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+ .tck = 8,
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+ .trcd = 20,
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+ .trp = 20,
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+ .twr = 8,
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ }, { /* Micron MT48LC8M16A2TG-75 */
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+ .name = "MT48LC8M16A2TG-75",
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+ .rows = 12,
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+ .tck = 8,
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+ .trcd = 20,
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+ .trp = 20,
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+ .twr = 8,
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+ .refresh = 64000,
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+ .cas_latency = 3,
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+ },
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+};
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+
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+static struct sdram_params sdram_params;
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+
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+/*
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+ * Given a period in ns and frequency in khz, calculate the number of
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+ * cycles of frequency in period. Note that we round up to the next
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+ * cycle, even if we are only slightly over.
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+ */
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+static inline u_int ns_to_cycles(u_int ns, u_int khz)
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+{
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+ return (ns * khz + 999999) / 1000000;
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+}
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+
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