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@@ -0,0 +1,76 @@
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+/*
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+ * OMAP MPUSS low power code
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+ *
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+ * Copyright (C) 2011 Texas Instruments, Inc.
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+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
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+ *
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+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
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+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
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+ * CPU0 and CPU1 LPRM modules.
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+ * CPU0, CPU1 and MPUSS each have there own power domain and
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+ * hence multiple low power combinations of MPUSS are possible.
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+ *
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+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
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+ * because the mode is not supported by hw constraints of dormant
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+ * mode. While waking up from the dormant mode, a reset signal
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+ * to the Cortex-A9 processor must be asserted by the external
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+ * power controller.
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+ *
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+ * With architectural inputs and hardware recommendations, only
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+ * below modes are supported from power gain vs latency point of view.
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+ *
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+ * CPU0 CPU1 MPUSS
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+ * ----------------------------------------------
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+ * ON ON ON
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+ * ON(Inactive) OFF ON(Inactive)
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+ * OFF OFF CSWR
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+ * OFF OFF OSWR
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+ * OFF OFF OFF(Device OFF *TBD)
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+ * ----------------------------------------------
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+ *
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+ * Note: CPU0 is the master core and it is the last CPU to go down
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+ * and first to wake-up when MPUSS low power states are excercised
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+ *
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/errno.h>
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+#include <linux/linkage.h>
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+#include <linux/smp.h>
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+
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+#include <asm/cacheflush.h>
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+#include <asm/tlbflush.h>
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+#include <asm/smp_scu.h>
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+#include <asm/pgalloc.h>
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+#include <asm/suspend.h>
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+#include <asm/hardware/cache-l2x0.h>
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+
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+#include "soc.h"
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+#include "common.h"
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+#include "omap44xx.h"
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+#include "omap4-sar-layout.h"
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+#include "pm.h"
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+#include "prcm_mpu44xx.h"
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+#include "prminst44xx.h"
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+#include "prcm44xx.h"
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+#include "prm44xx.h"
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+#include "prm-regbits-44xx.h"
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+
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+#ifdef CONFIG_SMP
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+
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+struct omap4_cpu_pm_info {
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+ struct powerdomain *pwrdm;
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+ void __iomem *scu_sar_addr;
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+ void __iomem *wkup_sar_addr;
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+ void __iomem *l2x0_sar_addr;
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+ void (*secondary_startup)(void);
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+};
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+
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+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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+static struct powerdomain *mpuss_pd;
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+static void __iomem *sar_base;
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