|  | @@ -194,3 +194,172 @@ static inline int
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				|  |  |  iop_chan_memset_slot_count(size_t len, int *slots_per_op)
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				|  |  |  {
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				|  |  |  	*slots_per_op = 1;
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				|  |  | +	return 1;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline int
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				|  |  | +iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
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				|  |  | +{
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				|  |  | +	static const char slot_count_table[] = { 1, 2, 2, 2,
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				|  |  | +						 2, 3, 3, 3,
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				|  |  | +						 3, 4, 4, 4,
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				|  |  | +						 4, 5, 5, 5,
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				|  |  | +						};
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				|  |  | +	*slots_per_op = slot_count_table[src_cnt - 1];
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				|  |  | +	return *slots_per_op;
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				|  |  | +}
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				|  |  | +
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				|  |  | +#define ADMA_MAX_BYTE_COUNT	(16 * 1024 * 1024)
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				|  |  | +#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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				|  |  | +#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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				|  |  | +#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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				|  |  | +#define IOP_ADMA_PQ_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
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				|  |  | +#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
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				|  |  | +#define iop_chan_pq_slot_count iop_chan_xor_slot_count
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				|  |  | +#define iop_chan_pq_zero_sum_slot_count iop_chan_xor_slot_count
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				|  |  | +
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				|  |  | +static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
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				|  |  | +					struct iop_adma_chan *chan)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	return hw_desc->dest_addr;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline u32 iop_desc_get_qdest_addr(struct iop_adma_desc_slot *desc,
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				|  |  | +					  struct iop_adma_chan *chan)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	return hw_desc->q_dest_addr;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
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				|  |  | +					struct iop_adma_chan *chan)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	return hw_desc->byte_count_field.byte_count;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
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				|  |  | +					struct iop_adma_chan *chan,
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				|  |  | +					int src_idx)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	return hw_desc->src[src_idx].src_addr;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
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				|  |  | +					struct iop_adma_chan *chan)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	return hw_desc->desc_ctrl_field.src_select + 1;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline void
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				|  |  | +iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = 0;
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				|  |  | +	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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				|  |  | +	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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				|  |  | +	hw_desc->desc_ctrl = u_desc_ctrl.value;
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				|  |  | +	hw_desc->crc_addr = 0;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline void
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				|  |  | +iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = 0;
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				|  |  | +	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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				|  |  | +	u_desc_ctrl.field.block_fill_en = 1;
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				|  |  | +	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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				|  |  | +	hw_desc->desc_ctrl = u_desc_ctrl.value;
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				|  |  | +	hw_desc->crc_addr = 0;
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				|  |  | +}
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				|  |  | +
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				|  |  | +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
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				|  |  | +static inline void
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				|  |  | +iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
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				|  |  | +		  unsigned long flags)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = 0;
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				|  |  | +	u_desc_ctrl.field.src_select = src_cnt - 1;
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				|  |  | +	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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				|  |  | +	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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				|  |  | +	hw_desc->desc_ctrl = u_desc_ctrl.value;
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				|  |  | +	hw_desc->crc_addr = 0;
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				|  |  | +
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				|  |  | +}
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				|  |  | +#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
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				|  |  | +
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				|  |  | +/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
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				|  |  | +static inline int
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				|  |  | +iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
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				|  |  | +		       unsigned long flags)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = 0;
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				|  |  | +	u_desc_ctrl.field.src_select = src_cnt - 1;
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				|  |  | +	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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				|  |  | +	u_desc_ctrl.field.zero_result = 1;
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				|  |  | +	u_desc_ctrl.field.status_write_back_en = 1;
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				|  |  | +	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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				|  |  | +	hw_desc->desc_ctrl = u_desc_ctrl.value;
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				|  |  | +	hw_desc->crc_addr = 0;
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				|  |  | +
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				|  |  | +	return 1;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline void
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				|  |  | +iop_desc_init_pq(struct iop_adma_desc_slot *desc, int src_cnt,
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				|  |  | +		  unsigned long flags)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = 0;
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				|  |  | +	u_desc_ctrl.field.src_select = src_cnt - 1;
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				|  |  | +	u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
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				|  |  | +	u_desc_ctrl.field.pq_xfer_en = 1;
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				|  |  | +	u_desc_ctrl.field.p_xfer_dis = !!(flags & DMA_PREP_PQ_DISABLE_P);
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				|  |  | +	u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
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				|  |  | +	hw_desc->desc_ctrl = u_desc_ctrl.value;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline int iop_desc_is_pq(struct iop_adma_desc_slot *desc)
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				|  |  | +{
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				|  |  | +	struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
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				|  |  | +	union {
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				|  |  | +		u32 value;
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				|  |  | +		struct iop13xx_adma_desc_ctrl field;
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				|  |  | +	} u_desc_ctrl;
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				|  |  | +
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				|  |  | +	u_desc_ctrl.value = hw_desc->desc_ctrl;
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				|  |  | +	return u_desc_ctrl.field.pq_xfer_en;
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				|  |  | +}
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				|  |  | +
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				|  |  | +static inline void
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