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@@ -999,3 +999,196 @@ typedef struct {
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#define LPICF BYTE_REF(LPICF_ADDR)
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#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */
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+#define LPICF_GS_BW 0x00
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+#define LPICF_GS_GRAY_4 0x01
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+#define LPICF_GS_GRAY_16 0x02
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+#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */
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+#define LPICF_PBSIZ_1 0x00
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+#define LPICF_PBSIZ_2 0x04
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+#define LPICF_PBSIZ_4 0x08
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+
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+/*
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+ * LCD Polarity Configuration Register
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+ */
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+#define LPOLCF_ADDR 0xfffffa21
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+#define LPOLCF BYTE_REF(LPOLCF_ADDR)
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+
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+#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */
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+#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */
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+#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */
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+#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */
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+
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+/*
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+ * LACD (LCD Alternate Crystal Direction) Rate Control Register
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+ */
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+#define LACDRC_ADDR 0xfffffa23
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+#define LACDRC BYTE_REF(LACDRC_ADDR)
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+
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+#define LACDRC_ACDSLT 0x80 /* Signal Source Select */
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+#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */
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+#define LACDRC_ACD_SHIFT 0
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+
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+/*
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+ * LCD Pixel Clock Divider Register
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+ */
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+#define LPXCD_ADDR 0xfffffa25
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+#define LPXCD BYTE_REF(LPXCD_ADDR)
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+
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+#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */
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+#define LPXCD_PCD_SHIFT 0
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+
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+/*
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+ * LCD Clocking Control Register
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+ */
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+#define LCKCON_ADDR 0xfffffa27
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+#define LCKCON BYTE_REF(LCKCON_ADDR)
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+
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+#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */
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+#define LCKCON_DWS_SHIFT 0
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+#define LCKCON_DWIDTH 0x40 /* Display Memory Width */
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+#define LCKCON_LCDON 0x80 /* Enable LCD Controller */
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+
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+/* '328-compatible definitions */
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+#define LCKCON_DW_MASK LCKCON_DWS_MASK
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+#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT
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+
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+/*
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+ * LCD Refresh Rate Adjustment Register
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+ */
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+#define LRRA_ADDR 0xfffffa29
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+#define LRRA BYTE_REF(LRRA_ADDR)
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+
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+/*
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+ * LCD Panning Offset Register
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+ */
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+#define LPOSR_ADDR 0xfffffa2d
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+#define LPOSR BYTE_REF(LPOSR_ADDR)
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+
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+#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */
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+#define LPOSR_POS_SHIFT 0
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+
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+/*
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+ * LCD Frame Rate Control Modulation Register
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+ */
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+#define LFRCM_ADDR 0xfffffa31
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+#define LFRCM BYTE_REF(LFRCM_ADDR)
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+
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+#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */
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+#define LFRCM_YMOD_SHIFT 0
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+#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */
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+#define LFRCM_XMOD_SHIFT 4
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+
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+/*
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+ * LCD Gray Palette Mapping Register
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+ */
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+#define LGPMR_ADDR 0xfffffa33
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+#define LGPMR BYTE_REF(LGPMR_ADDR)
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+
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+#define LGPMR_G1_MASK 0x0f
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+#define LGPMR_G1_SHIFT 0
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+#define LGPMR_G2_MASK 0xf0
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+#define LGPMR_G2_SHIFT 4
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+
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+/*
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+ * PWM Contrast Control Register
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+ */
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+#define PWMR_ADDR 0xfffffa36
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+#define PWMR WORD_REF(PWMR_ADDR)
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+
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+#define PWMR_PW_MASK 0x00ff /* Pulse Width */
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+#define PWMR_PW_SHIFT 0
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+#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */
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+#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */
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+#define PWMR_SRC_LINE 0x0000 /* Line Pulse */
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+#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */
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+#define PWMR_SRC_LCD 0x4000 /* LCD clock */
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+
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+/**********
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+ *
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+ * 0xFFFFFBxx -- Real-Time Clock (RTC)
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+ *
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+ **********/
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+
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+/*
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+ * RTC Hours Minutes and Seconds Register
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+ */
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+#define RTCTIME_ADDR 0xfffffb00
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+#define RTCTIME LONG_REF(RTCTIME_ADDR)
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+
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+#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */
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+#define RTCTIME_SECONDS_SHIFT 0
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+#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */
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+#define RTCTIME_MINUTES_SHIFT 16
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+#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */
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+#define RTCTIME_HOURS_SHIFT 24
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+
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+/*
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+ * RTC Alarm Register
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+ */
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+#define RTCALRM_ADDR 0xfffffb04
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+#define RTCALRM LONG_REF(RTCALRM_ADDR)
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+
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+#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */
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+#define RTCALRM_SECONDS_SHIFT 0
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+#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */
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+#define RTCALRM_MINUTES_SHIFT 16
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+#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */
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+#define RTCALRM_HOURS_SHIFT 24
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+
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+/*
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+ * Watchdog Timer Register
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+ */
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+#define WATCHDOG_ADDR 0xfffffb0a
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+#define WATCHDOG WORD_REF(WATCHDOG_ADDR)
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+
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+#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */
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+#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */
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+#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occurred */
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+#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */
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+#define WATCHDOG_CNT_SHIFT 8
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+
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+/*
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+ * RTC Control Register
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+ */
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+#define RTCCTL_ADDR 0xfffffb0c
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+#define RTCCTL WORD_REF(RTCCTL_ADDR)
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+
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+#define RTCCTL_XTL 0x0020 /* Crystal Selection */
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+#define RTCCTL_EN 0x0080 /* RTC Enable */
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+
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+/* '328-compatible definitions */
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+#define RTCCTL_384 RTCCTL_XTL
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+#define RTCCTL_ENABLE RTCCTL_EN
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+
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+/*
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+ * RTC Interrupt Status Register
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+ */
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+#define RTCISR_ADDR 0xfffffb0e
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+#define RTCISR WORD_REF(RTCISR_ADDR)
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+
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+#define RTCISR_SW 0x0001 /* Stopwatch timed out */
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+#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */
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+#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */
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+#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */
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+#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */
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+#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */
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+#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */
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+#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */
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+#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */
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+#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */
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+#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */
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+#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */
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+#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */
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+#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */
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+
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+/*
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+ * RTC Interrupt Enable Register
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+ */
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+#define RTCIENR_ADDR 0xfffffb10
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+#define RTCIENR WORD_REF(RTCIENR_ADDR)
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+
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+#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */
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+#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */
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+#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */
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+#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */
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+#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */
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