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@@ -1157,3 +1157,76 @@
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#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
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#define HOST_STATUS 0xffc03404 /* HOST Status Register */
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#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
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+
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+/* Counter Registers */
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+
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+#define CNT_CONFIG 0xffc03500 /* Configuration Register */
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+#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
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+#define CNT_STATUS 0xffc03508 /* Status Register */
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+#define CNT_COMMAND 0xffc0350c /* Command Register */
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+#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
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+#define CNT_COUNTER 0xffc03514 /* Counter Register */
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+#define CNT_MAX 0xffc03518 /* Maximal Count Register */
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+#define CNT_MIN 0xffc0351c /* Minimal Count Register */
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+
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+/* OTP/FUSE Registers */
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+
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+#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
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+#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
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+#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
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+#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
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+
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+/* Security Registers */
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+
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+#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
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+#define SECURE_CONTROL 0xffc03624 /* Secure Control */
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+#define SECURE_STATUS 0xffc03628 /* Secure Status */
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+
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+/* OTP Read/Write Data Buffer Registers */
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+
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+#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
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+
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+/* NFC Registers */
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+
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+#define NFC_CTL 0xffc03700 /* NAND Control Register */
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+#define NFC_STAT 0xffc03704 /* NAND Status Register */
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+#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
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+#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
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+#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
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+#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
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+#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
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+#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
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+#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
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+#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
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+#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
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+#define NFC_READ 0xffc0372c /* NAND Read Data Register */
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+#define NFC_ADDR 0xffc03740 /* NAND Address Register */
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+#define NFC_CMD 0xffc03744 /* NAND Command Register */
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+#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
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+#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
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+
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+/* ********************************************************** */
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+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
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+/* and MULTI BIT READ MACROS */
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+/* ********************************************************** */
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+
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+/* Bit masks for HOST_CONTROL */
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+
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+#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */
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+#define HOST_CNTR_nHOST_EN 0x0
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+#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */
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+#define HOST_CNTR_nHOST_END 0x0
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+#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */
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+#define HOST_CNTR_nDATA_SIZE 0x0
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+#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */
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+#define HOST_CNTR_nHOST_RST 0x0
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+#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */
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+#define HOST_CNTR_nHRDY_OVR 0x0
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+#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */
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+#define HOST_CNTR_nINT_MODE 0x0
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+#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */
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+#define HOST_CNTR_ nBT_EN 0x0
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+#define HOST_CNTR_EHW 0x100 /* Enable Host Write */
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