|
@@ -134,3 +134,60 @@
|
|
|
#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
|
|
|
#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
|
|
|
#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
|
|
|
+#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
|
|
|
+#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
|
|
|
+#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
|
|
|
+#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
|
|
|
+#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
|
|
|
+#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
|
|
|
+#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
|
|
|
+#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
|
|
|
+#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
|
|
|
+#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
|
|
|
+#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
|
|
|
+#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
|
|
|
+#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
|
|
|
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
|
|
|
+#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
|
|
|
+#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
|
|
|
+
|
|
|
+/* Two Wire Interface Registers (TWI1) */
|
|
|
+
|
|
|
+/* SPI2 Registers */
|
|
|
+
|
|
|
+#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
|
|
|
+#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
|
|
|
+#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
|
|
|
+#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
|
|
|
+#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
|
|
|
+#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
|
|
|
+#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
|
|
|
+#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
|
|
|
+#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
|
|
|
+#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
|
|
|
+#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
|
|
|
+#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
|
|
|
+#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
|
|
|
+#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
|
|
|
+
|
|
|
+/* ATAPI Registers */
|
|
|
+
|
|
|
+#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
|
|
|
+#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
|
|
|
+#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
|
|
|
+#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
|
|
|
+#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
|
|
|
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
|
|
|
+#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
|
|
|
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
|
|
|
+#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
|
|
|
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
|
|
|
+#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
|
|
|
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
|
|
|
+#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
|
|
|
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
|
|
|
+#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
|
|
|
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
|
|
|
+#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
|
|
|
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
|
|
|
+#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
|