|
|
@@ -194,3 +194,150 @@ extern unsigned long get_iop_tick_rate(void);
|
|
|
IQ81340_NUM_PHYS_MAP_FLASH + \
|
|
|
IQ81340_NUM_ADMA)
|
|
|
|
|
|
+/*========================== PMMR offsets for key registers ============*/
|
|
|
+#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
|
|
|
+#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
|
|
|
+#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
|
|
|
+#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
|
|
|
+#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
|
|
|
+#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
|
|
|
+#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
|
|
|
+#define IOP13XX_MU_PMMR_OFFSET 0x00004000
|
|
|
+#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
|
|
|
+#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
|
|
|
+
|
|
|
+#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
|
|
|
+#define IOP13XX_CONTROLLER_ONLY (1 << 14)
|
|
|
+#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
|
|
|
+
|
|
|
+#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
|
|
|
+#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
|
|
|
+ IOP13XX_PMON_PMMR_OFFSET)
|
|
|
+#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
|
|
|
+ IOP13XX_PMON_PMMR_OFFSET)
|
|
|
+
|
|
|
+#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
|
|
|
+#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
|
|
|
+#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
|
|
|
+#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
|
|
|
+
|
|
|
+#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
|
|
|
+#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
|
|
|
+#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
|
|
|
+#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
|
|
|
+
|
|
|
+#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
|
|
|
+#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
|
|
|
+#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
|
|
|
+#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
|
|
|
+
|
|
|
+#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
|
|
|
+#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
|
|
|
+
|
|
|
+/*================================ATU===================================*/
|
|
|
+#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
|
|
|
+ iop13xx_atux_pmmr_offset + (ofs))
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atux_pmmr_offset + 0x2)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atux_pmmr_offset + 0x4)
|
|
|
+#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atux_pmmr_offset + 0x6)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
|
|
|
+#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
|
|
|
+#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
|
|
|
+#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
|
|
|
+#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
|
|
|
+#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
|
|
|
+#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
|
|
|
+#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
|
|
|
+#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
|
|
|
+#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
|
|
|
+#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
|
|
|
+#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
|
|
|
+#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
|
|
|
+#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
|
|
|
+#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
|
|
|
+#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
|
|
|
+#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
|
|
|
+#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
|
|
|
+#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
|
|
|
+#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
|
|
|
+#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
|
|
|
+#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
|
|
|
+#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
|
|
|
+#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
|
|
|
+#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
|
|
|
+#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
|
|
|
+#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
|
|
|
+#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
|
|
|
+#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
|
|
|
+#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
|
|
|
+#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
|
|
|
+#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
|
|
|
+#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
|
|
|
+#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
|
|
|
+#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
|
|
|
+#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
|
|
|
+#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
|
|
|
+#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
|
|
|
+#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
|
|
|
+#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
|
|
|
+#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
|
|
|
+#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
|
|
|
+#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
|
|
|
+#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
|
|
|
+#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
|
|
|
+#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
|
|
|
+#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
|
|
|
+#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
|
|
|
+#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
|
|
|
+#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
|
|
|
+#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
|
|
|
+#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
|
|
|
+#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
|
|
|
+#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
|
|
|
+#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
|
|
|
+#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
|
|
|
+#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
|
|
|
+#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
|
|
|
+#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
|
|
|
+#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
|
|
|
+
|
|
|
+#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
|
|
|
+#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
|
|
|
+
|
|
|
+#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
|
|
|
+ iop13xx_atue_pmmr_offset + (ofs))
|
|
|
+
|
|
|
+#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atue_pmmr_offset + 0x2)
|
|
|
+#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atue_pmmr_offset + 0x4)
|
|
|
+#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
|
|
|
+ iop13xx_atue_pmmr_offset + 0x6)
|
|
|
+
|
|
|
+#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
|
|
|
+#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
|
|
|
+#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
|
|
|
+#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
|
|
|
+#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
|
|
|
+#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
|
|
|
+#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
|
|
|
+#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
|
|
|
+#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
|
|
|
+#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
|
|
|
+#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
|
|
|
+#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
|
|
|
+#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
|
