|
|
@@ -128,3 +128,54 @@ struct bfin_eppi3_regs {
|
|
|
#define EPPI_CTL_POLS 0x0000C000 /* Frame Sync Polarity */
|
|
|
#define EPPI_CTL_FS1HI_FS2HI 0x00000000 /* POLS: FS1 and FS2 are active high */
|
|
|
#define EPPI_CTL_FS1LO_FS2HI 0x00004000 /* POLS: FS1 is active low. FS2 is active high */
|
|
|
+#define EPPI_CTL_FS1HI_FS2LO 0x00008000 /* POLS: FS1 is active high. FS2 is active low */
|
|
|
+#define EPPI_CTL_FS1LO_FS2LO 0x0000C000 /* POLS: FS1 and FS2 are active low */
|
|
|
+#define EPPI_CTL_DLEN 0x00070000 /* Data Length */
|
|
|
+#define EPPI_CTL_DLEN08 0x00000000 /* DLEN: 8 bits */
|
|
|
+#define EPPI_CTL_DLEN10 0x00010000 /* DLEN: 10 bits */
|
|
|
+#define EPPI_CTL_DLEN12 0x00020000 /* DLEN: 12 bits */
|
|
|
+#define EPPI_CTL_DLEN14 0x00030000 /* DLEN: 14 bits */
|
|
|
+#define EPPI_CTL_DLEN16 0x00040000 /* DLEN: 16 bits */
|
|
|
+#define EPPI_CTL_DLEN18 0x00050000 /* DLEN: 18 bits */
|
|
|
+#define EPPI_CTL_DLEN20 0x00060000 /* DLEN: 20 bits */
|
|
|
+#define EPPI_CTL_DLEN24 0x00070000 /* DLEN: 24 bits */
|
|
|
+#define EPPI_CTL_DMIRR 0x00080000 /* Data Mirroring */
|
|
|
+#define EPPI_CTL_SKIPEN 0x00100000 /* Skip Enable */
|
|
|
+#define EPPI_CTL_SKIPEO 0x00200000 /* Skip Even or Odd */
|
|
|
+#define EPPI_CTL_PACKEN 0x00400000 /* Pack/Unpack Enable */
|
|
|
+#define EPPI_CTL_SWAPEN 0x00800000 /* Swap Enable */
|
|
|
+#define EPPI_CTL_SPLTEO 0x01000000 /* Split Even and Odd Data Samples */
|
|
|
+#define EPPI_CTL_SUBSPLTODD 0x02000000 /* Sub-Split Odd Samples */
|
|
|
+#define EPPI_CTL_SPLTWRD 0x04000000 /* Split Word */
|
|
|
+#define EPPI_CTL_RGBFMTEN 0x08000000 /* RGB Formatting Enable */
|
|
|
+#define EPPI_CTL_DMACFG 0x10000000 /* One or Two DMA Channels Mode */
|
|
|
+#define EPPI_CTL_DMAFINEN 0x20000000 /* DMA Finish Enable */
|
|
|
+#define EPPI_CTL_MUXSEL 0x40000000 /* MUX Select */
|
|
|
+#define EPPI_CTL_CLKGATEN 0x80000000 /* Clock Gating Enable */
|
|
|
+
|
|
|
+#define EPPI_FS2_WLVB_F2VBAD 0xFF000000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking after field 2 */
|
|
|
+#define EPPI_FS2_WLVB_F2VBBD 0x00FF0000 /* In GP transmit mode with BLANKGEN = 1, contains number of lines of vertical blanking before field 2 */
|
|
|
+#define EPPI_FS2_WLVB_F1VBAD 0x0000FF00 /* In GP transmit mode with, BLANKGEN = 1, contains number of lines of vertical blanking after field 1 */
|
|
|
+#define EPPI_FS2_WLVB_F1VBBD 0x000000FF /* In GP 2, or 3 FS modes used to generate PPIx_FS2 width (32-bit). In GP Transmit mode, with BLANKGEN=1, contains the number of lines of Vertical blanking before field 1. */
|
|
|
+
|
|
|
+#define EPPI_FS2_PALPF_F2ACT 0xFFFF0000 /* Number of lines of Active Data in Field 2 */
|
|
|
+#define EPPI_FS2_PALPF_F1ACT 0x0000FFFF /* Number of lines of Active Data in Field 1 */
|
|
|
+
|
|
|
+#define EPPI_IMSK_CFIFOERR 0x00000001 /* Mask CFIFO Underflow or Overflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_YFIFOERR 0x00000002 /* Mask YFIFO Underflow or Overflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_LTERROVR 0x00000004 /* Mask Line Track Overflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_LTERRUNDR 0x00000008 /* Mask Line Track Underflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_FTERROVR 0x00000010 /* Mask Frame Track Overflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_FTERRUNDR 0x00000020 /* Mask Frame Track Underflow Error Interrupt */
|
|
|
+#define EPPI_IMSK_ERRNCOR 0x00000040 /* Mask ITU Preamble Error Not Corrected Interrupt */
|
|
|
+#define EPPI_IMSK_PXPERR 0x00000080 /* Mask PxP Ready Error Interrupt */
|
|
|
+
|
|
|
+#define EPPI_ODDCLIP_HIGHODD 0xFFFF0000
|
|
|
+#define EPPI_ODDCLIP_LOWODD 0x0000FFFF
|
|
|
+
|
|
|
+#define EPPI_EVENCLIP_HIGHEVEN 0xFFFF0000
|
|
|
+#define EPPI_EVENCLIP_LOWEVEN 0x0000FFFF
|
|
|
+
|
|
|
+#define EPPI_CTL2_FS1FINEN 0x00000002 /* HSYNC Finish Enable */
|
|
|
+#endif
|
|
|
+#endif
|
徐寅秋