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+#ifndef _ASM_IA64_PAL_H
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+#define _ASM_IA64_PAL_H
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+
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+/*
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+ * Processor Abstraction Layer definitions.
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+ *
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+ * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
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+ * chapter 11 IA-64 Processor Abstraction Layer
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+ *
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+ * Copyright (C) 1998-2001 Hewlett-Packard Co
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+ * David Mosberger-Tang <davidm@hpl.hp.com>
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+ * Stephane Eranian <eranian@hpl.hp.com>
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+ * Copyright (C) 1999 VA Linux Systems
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+ * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
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+ * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
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+ * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
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+ *
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+ * 99/10/01 davidm Make sure we pass zero for reserved parameters.
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+ * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
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+ * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
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+ * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
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+ * 00/05/25 eranian Support for stack calls, and static physical calls
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+ * 00/06/18 eranian Support for stacked physical calls
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+ * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
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+ * Manual Rev 2.2 (Jan 2006)
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+ */
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+
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+/*
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+ * Note that some of these calls use a static-register only calling
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+ * convention which has nothing to do with the regular calling
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+ * convention.
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+ */
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+#define PAL_CACHE_FLUSH 1 /* flush i/d cache */
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+#define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
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+#define PAL_CACHE_INIT 3 /* initialize i/d cache */
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+#define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */
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+#define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
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+#define PAL_PTCE_INFO 6 /* purge TLB info */
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+#define PAL_VM_INFO 7 /* return supported virtual memory features */
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+#define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
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+#define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
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+#define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
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+#define PAL_DEBUG_INFO 11 /* get number of debug registers */
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+#define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
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+#define PAL_FREQ_BASE 13 /* base frequency of the platform */
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+#define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
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+#define PAL_PERF_MON_INFO 15 /* return performance monitor info */
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+#define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
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+#define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
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+#define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
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+#define PAL_RSE_INFO 19 /* return rse information */
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+#define PAL_VERSION 20 /* return version of PAL code */
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+#define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
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+#define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
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+#define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
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+#define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
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+#define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
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+#define PAL_MC_RESUME 26 /* Return to interrupted process */
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+#define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
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+#define PAL_HALT 28 /* enter the low power HALT state */
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+#define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
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+#define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
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+#define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
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+#define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
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+#define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
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+#define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
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+
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+#define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
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+#define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
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+#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
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+#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
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+#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
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+#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
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+#define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
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+#define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
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+#define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
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+#define PAL_VP_INFO 50 /* Information about virtual processor features */
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+#define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
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+
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+#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
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+#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
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+#define PAL_TEST_PROC 258 /* perform late processor self-test */
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+#define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
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+#define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
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+#define PAL_VM_TR_READ 261 /* read contents of translation register */
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+#define PAL_GET_PSTATE 262 /* get the current P-state */
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+#define PAL_SET_PSTATE 263 /* set the P-state */
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+#define PAL_BRAND_INFO 274 /* Processor branding information */
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+
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+#define PAL_GET_PSTATE_TYPE_LASTSET 0
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+#define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
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+#define PAL_GET_PSTATE_TYPE_AVGNORESET 2
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+#define PAL_GET_PSTATE_TYPE_INSTANT 3
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+
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+#define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
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+
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+#ifndef __ASSEMBLY__
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+
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+#include <linux/types.h>
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+#include <asm/fpu.h>
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+
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+/*
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+ * Data types needed to pass information into PAL procedures and
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+ * interpret information returned by them.
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+ */
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+
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+/* Return status from the PAL procedure */
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+typedef s64 pal_status_t;
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+
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+#define PAL_STATUS_SUCCESS 0 /* No error */
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+#define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
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+#define PAL_STATUS_EINVAL (-2) /* Invalid argument */
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+#define PAL_STATUS_ERROR (-3) /* Error */
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+#define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
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+ * specified level and type of
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+ * cache without sideeffects
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+ * and "restrict" was 1
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+ */
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+#define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
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+
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+/* Processor cache level in the hierarchy */
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+typedef u64 pal_cache_level_t;
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+#define PAL_CACHE_LEVEL_L0 0 /* L0 */
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+#define PAL_CACHE_LEVEL_L1 1 /* L1 */
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+#define PAL_CACHE_LEVEL_L2 2 /* L2 */
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+
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+
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+/* Processor cache type at a particular level in the hierarchy */
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+
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+typedef u64 pal_cache_type_t;
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+#define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
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+#define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
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+#define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
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+
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+
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+#define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
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+#define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
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+
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+/* Processor cache line size in bytes */
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+typedef int pal_cache_line_size_t;
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+
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+/* Processor cache line state */
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+typedef u64 pal_cache_line_state_t;
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+#define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
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+#define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
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+#define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
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+#define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
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+
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+typedef struct pal_freq_ratio {
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+ u32 den, num; /* numerator & denominator */
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+} itc_ratio, proc_ratio;
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+
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+typedef union pal_cache_config_info_1_s {
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+ struct {
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+ u64 u : 1, /* 0 Unified cache ? */
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+ at : 2, /* 2-1 Cache mem attr*/
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+ reserved : 5, /* 7-3 Reserved */
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+ associativity : 8, /* 16-8 Associativity*/
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+ line_size : 8, /* 23-17 Line size */
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+ stride : 8, /* 31-24 Stride */
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+ store_latency : 8, /*39-32 Store latency*/
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+ load_latency : 8, /* 47-40 Load latency*/
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+ store_hints : 8, /* 55-48 Store hints*/
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+ load_hints : 8; /* 63-56 Load hints */
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+ } pcci1_bits;
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+ u64 pcci1_data;
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+} pal_cache_config_info_1_t;
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+
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+typedef union pal_cache_config_info_2_s {
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+ struct {
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+ u32 cache_size; /*cache size in bytes*/
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+
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+
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+ u32 alias_boundary : 8, /* 39-32 aliased addr
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+ * separation for max
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+ * performance.
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+ */
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+ tag_ls_bit : 8, /* 47-40 LSb of addr*/
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+ tag_ms_bit : 8, /* 55-48 MSb of addr*/
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+ reserved : 8; /* 63-56 Reserved */
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+ } pcci2_bits;
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+ u64 pcci2_data;
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+} pal_cache_config_info_2_t;
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+
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+
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+typedef struct pal_cache_config_info_s {
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+ pal_status_t pcci_status;
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+ pal_cache_config_info_1_t pcci_info_1;
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+ pal_cache_config_info_2_t pcci_info_2;
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+ u64 pcci_reserved;
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+} pal_cache_config_info_t;
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+
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+#define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
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+#define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
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+#define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
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+#define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
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+#define pcci_stride pcci_info_1.pcci1_bits.stride
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+#define pcci_line_size pcci_info_1.pcci1_bits.line_size
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+#define pcci_assoc pcci_info_1.pcci1_bits.associativity
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袁开兴