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				|  |  | +/*
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				|  |  | + * Copyright 2011 Analog Devices Inc.
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				|  |  | + *
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				|  |  | + * Licensed under the GPL-2 or later
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				|  |  | + */
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				|  |  | +
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				|  |  | +#ifndef _MACH_PORTMUX_H_
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				|  |  | +#define _MACH_PORTMUX_H_
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				|  |  | +
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				|  |  | +#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
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				|  |  | +
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				|  |  | +/* EMAC RMII Port Mux */
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				|  |  | +#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
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				|  |  | +#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
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				|  |  | +#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
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				|  |  | +#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
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				|  |  | +#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
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				|  |  | +#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
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				|  |  | +
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