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				@@ -565,3 +565,23 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { 
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				 		}, 
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				 	}, 
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				 	.class		= &omap2_uart_class, 
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				+}; 
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				+ 
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				+static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { 
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				+	{ .irq = 84 + OMAP_INTC_START, }, 
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				+	{ .irq = -1 }, 
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				+}; 
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				+ 
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				+static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { 
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				+	{ .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, 
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				+	{ .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, 
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				+	{ .dma_req = -1 } 
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				+}; 
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				+ 
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				+/* 
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				+ * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or 
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				+ * uart2_fck being enabled.  So we add uart1_fck as an optional clock, 
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				+ * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really 
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				+ * should not be needed.  The functional clock structure of the AM35xx 
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				+ * UART4 is extremely unclear and opaque; it is unclear what the role 
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				+ * of uart1/2_fck is for the UART4.  Any clarification from either 
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